A super parallel vision system implemented with mixed analog and digital circuits
| Project/Area Number |
14350188
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
電子デバイス・機器工学
|
|---|
| Research Institution | Osaka University |
|---|
Principal Investigator |
YAGI Tetsuya Gradutate School of Eng., Electronic Eng., Professor, 大学院・工学研究科, 教授 (50183976)
|
|---|
| Project Period (FY) |
2002 – 2003
|
| Project Status |
Completed (Fiscal Year 2003)
|
| Budget Amount *help |
¥13,600,000 (Direct Cost: ¥13,600,000)
Fiscal Year 2003: ¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 2002: ¥7,800,000 (Direct Cost: ¥7,800,000)
|
|---|
| Keywords | retina / image processing / analog VLS / real time processing / robot vision / parallel vision / FPGA / multi-media / シリコン網膜 / 実時間 / 静止画像 / 動画像 / 運動方向検出 / 奥行き検出 |
|---|
| Research Abstract |
The purpose of the present research is to develop a novel vision system that can carry out the real-time image processing with mixed analog/digital architecture. Accordingly, we have designed and fabricated the system consisting of a silicon retina, an analog Very Large Scale Integrated (VLSI) circuit and Field Programmable Gate Array. (FPGA). The silicon retina emulates the sustained and the transient responses found in the vertebrate retina. The output emulating sustained response possesses a Palladian-Gaussian-like receptive field and therefore carries out a smoothing and contrast-enhancement on input images. The output emulating the transient response was obtained by subtracting consecutive images that were smoothed out by the resistive network. The outputs of these two channels can be obtained alternately from the silicon retina in real time, within time delays not exceeding a few tens of ms, in indoor illumination. The outputs of the chip are offset-suppressed analog voltages since uncontrollable mismatches of transistor characteristics are compensated for with the aid of sample/hold circuits embedded in each pixel circuit. The analog outputs from the silicon retina representing the preprocessed image with these channels are transferred to the FPGA through a A/D converter. The FPGA carries out digital image computations such as edge detection, target tracking and depth perception. The parallel vision system developed in the present study is readily used in a variety of engineering applications such as the fields of robot vision and multi-media.
|
Report
(3 results)
Research Products
(12 results)
