| Project/Area Number |
14380131
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
NAKAMURA Tadao Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (80005454)
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| Co-Investigator(Kenkyū-buntansha) |
GOTO Gensuke Yamagata University, Faculty of Engineering, Professor, 工学部, 教授 (80333988)
FUKASE Masaaki Hirosaki University, Faculty of Science and Technology, Professor, 理工学部, 教授 (10125643)
KOBAYASHI Hiroaki Tohoku University, Information Synergy Center, Professor, 情報シナジーセンター, 教授 (40205480)
HAGIWARA Masafumi Keio University, Faculty of Science and Technology, Professor, 理工学部, 教授 (80198655)
SUZUKI Ken-ichi Tohoku University, Graduate School of Information Sciences, Lecturer, 大学院・情報科学研究科, 講師 (50300520)
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥14,900,000 (Direct Cost: ¥14,900,000)
Fiscal Year 2004: ¥4,400,000 (Direct Cost: ¥4,400,000)
Fiscal Year 2003: ¥3,300,000 (Direct Cost: ¥3,300,000)
Fiscal Year 2002: ¥7,200,000 (Direct Cost: ¥7,200,000)
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| Keywords | Microprocessors / Computer Architecture / Low-power Ultra high-speed / VLSI |
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| Research Abstract |
In the recent decades, the performance improvement of microprocessors has been achieved, resulting in the increase of power consumption of processors, which causes the serious thermal problem on a chip. Nevertheless, since the strong demand for low power and high performance processors still exists, an architecture of microprocessors to solve the problem is required. In this research, our objective has been to establish microprocessor architectures enabling low power and low frequency operation by composing their modules reasonably. Firstly, we have shown a direction of future microprocessor design by defining the conception of its low power and high speed operation. This direction is so revolutionary that the head investigator has been and is going to be asked to be an invited speaker at international conferences.
Based on the definition, we have proposed and evaluated some architectures for low power microprocessors. We also have shown that fine and course grain parallelism in threads should be extracted from application programs to exploit the feature of the proposed architectures, and further have implemented the method to obtain the parallelism from programs.
On the other hand, in order to achieve low power and high speed microprocessors, it is essential to design their datapaths. We have designed a datapath by using wave pipelining, which enables both high speed processing and low power operation. In addition, we have proposed a new cache mechanism to bridge the speed gap between the datapath of a microprocessor and the main memory.
As an application of parallel processing, designing codebooks for compressing information is well-known. We have challenged to this application by investigating the possibility of reducing the power consumption from the viewpoints of both software and hardware. We have shown the effectiveness of our architecture by implementing low power and high speed parallel dedicated processors.
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