| Project/Area Number |
14380132
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Tohoku University |
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Principal Investigator |
KOBAYASHI Hiroaki Tohoku University, Information Synergy Center, Professor, 情報シナジーセンター, 教授 (40205480)
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| Co-Investigator(Kenkyū-buntansha) |
NAKAMURA Tadao Tohoku University, Graduate School of Information Sciences, Professor, 大学院・情報科学研究科, 教授 (80005454)
SUZUKI Ken-ichi Tohoku University, Graduate School of Information Sciences, Lecturer, 大学院・情報科学研究科, 講師 (50300520)
TAKIZAWA Hiroyuki Tohoku University, Graduate School of Information Sciences, Lecturer, 大学院・情報科学研究科, 講師 (70323996)
SANO Kentaro Tohoku University, Graduate School of Information Sciences, Research Associate, 大学院・情報科学研究科, 助手 (00323048)
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥8,200,000 (Direct Cost: ¥8,200,000)
Fiscal Year 2004: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2003: ¥2,900,000 (Direct Cost: ¥2,900,000)
Fiscal Year 2002: ¥3,100,000 (Direct Cost: ¥3,100,000)
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| Keywords | Memory System / Graphics Hardware / Photo-Realistic Image Synthesis / Power-Aware Computing / Media Processor / Real-Time Ray Tracing / Data Compression / Vector Quantization / グラフィックスプロセッサ / 大域照明モデル / システムLSI / レンダリングパイプライン |
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| Research Abstract |
We have the following achievements
(1)High-performance graphics algorithm and its hardware
We analyzed parallelism and locality of reference in a graphics algorithm based on the global illumination model, and designed a novel rendering pipeline architecture for this algorithm. In addition, we designed and developed a prototype hardware based on the architecture. Through the performance evaluation of the hardware, we showed its effectiveness for realizing interactive ray-tracing. Moreover, we designed a new high-performance algorithm for generating walkthrough animations.
(2)Power-efficient memory mechanism
For design of the intelligent memory architecture for mobile devices, a low-power mechanism for on-chip memory system was designed. In this mechanism, memory modules are activated and inactivated based on their activity during the program execution. We clarified the relationship between activated memory modules and sustained performance, and showed the effectiveness of power-aware computing for on-chip cache memory.
(3)Data compression algorithms for graphics hardware.
We applied vector quantization to volume data set to achieve efficient data compression, and designed a visualization algorithm that can directly visualize the compressed volume data. We also designed a novel data compression algorithm using data clustering for graphics hardware
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