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Low-Power and High-Performance Processor based on Co-optimization of Architecture and Compiler

Research Project

Project/Area Number 14380136
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field 計算機科学
Research InstitutionThe University of Tokyo

Principal Investigator

NAKAMURA Hiroshi  The University of Tokyo, Research Center for Advanced Science and Technology, Associate Professor, 先端科学技術研究センター, 助教授 (20212102)

Co-Investigator(Kenkyū-buntansha) NANYA Takashi  The University of Tokyo, Research Center for Advanced Science and Technology, Professor, 先端科学技術研究センター, 教授 (80143684)
SATO Mitsuhisa  University of Tsukuba, Graduate School of Systems and Information Engineering, Professor, システム情報工学研究科, 教授 (60333481)
Project Period (FY) 2002 – 2005
Project Status Completed (Fiscal Year 2005)
Budget Amount *help
¥16,500,000 (Direct Cost: ¥16,500,000)
Fiscal Year 2005: ¥2,400,000 (Direct Cost: ¥2,400,000)
Fiscal Year 2004: ¥3,400,000 (Direct Cost: ¥3,400,000)
Fiscal Year 2003: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 2002: ¥6,400,000 (Direct Cost: ¥6,400,000)
KeywordsProcessor Architecture / Memory Hierarchy / Software Controlled Memory / Low Power Consumption / Compiler / Dynamic Power / Static Power / Register / 低消費電力プロセッサ / ダイナミック消費エネルギー / スタティック消費エネルギー / リーク電流 / 温度依存最適化 / レジスタファイル / 動的消費電力 / 静的消費電力 / 計算機アーキテクチャ / メモリシステム / マイクロプロセッサ / コンパイル技術 / キャッシュメモリ / 計算機アークテクチャ
Research Abstract

The purpose of this research is to achieve high performance and low power consumption by using compiler optimization on the usage of memory hierarchy. First, we proposed a new memory architecture which implements both software controlled memory and cache memory on a processor chip. By using the software controlled memory, compiler can optimize the data transfer between memory hierarchies and reduce power-wasting off-chip memory traffic. A new mechanism of register file is also proposed to reduce power consumption with little performance degradation. Second, we proposed a mechanism to shut down the voltage supply of the above new memory with fine granularity. Third, we developed a new compilation algorithm which co-operates with the above architecture for higher performance and lower power consumption. Energy consumption of a processor consists of dynamic energy and static energy. Because these two terms depend on the usage ration of software controlled memory independently, the least energy cannot be derived by minimizing either of them. Furthermore, static energy heavily depends on temperature. Thus, we propose a a new temperature aware compilation technique. The technique pre-computes the relationship between the memory usage ratio and operating temperature. Then, given source codes are optimized to select the best memory usage ratio dynamically by monitoring the operating temperature and by using the pre-computed relationship. We developed an environment to evaluate the effectiveness of our architecture and compilation algorithm. The evaluation results revealed that our co-optimization strategy can successfully reduce power consumption and achieve high performance.

Report

(5 results)
  • 2005 Annual Research Report   Final Research Report Summary
  • 2004 Annual Research Report
  • 2003 Annual Research Report
  • 2002 Annual Research Report
  • Research Products

    (31 results)

All 2006 2005 2004 2003 Other

All Journal Article (21 results) Publications (10 results)

  • [Journal Article] A Temperature Aware Compilation for Software-Controlled On-Chip Memory Architecture2006

    • Author(s)
      M.Fujita, M.Kondo, H.Nakamura
    • Journal Title

      Proc. of 4th Workshop on Optimizations for DSP and Embedded Systems

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] A Temperature Aware Compilation for Software-Controlled On-chip Memory Architecture2006

    • Author(s)
      M.Fujita, M.Kondo, H.Nakamura
    • Journal Title

      Proc. of 4th Workshop on Optimizations for DSP and Embedded Systems Mar.

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] A Temperature Aware Compilation for Software-Controlled On-chip Memory Architecture2006

    • Author(s)
      M.Fujita, M.Kondo, H.Nakamura
    • Journal Title

      ODES-4 (Workshop on Optimizations for DSP and Embedded Systems)

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Small, Fast and Low-Power Register File by Bit-Partitioning2005

    • Author(s)
      M.Kondo, H.Nakanura
    • Journal Title

      Proc. of HPCA-11

      Pages: 40-49

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Small, Fast and Low-Power Register File by Bit-Partitioning2005

    • Author(s)
      M.Kondo, H.Nakamura
    • Journal Title

      Proc. of 11th Symposium on High Performance Computer Architecture (HPCA-11) Feb.

      Pages: 40-49

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] ビット分割構成によるレジスタファイルのサイズおよびポート数削減手法2005

    • Author(s)
      近藤正章, 中村宏
    • Journal Title

      先進的計算基盤システムシンポジウムSACSIS2005

      Pages: 115-122

    • NAID

      110002769824

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 高性能計算のための低電力・高密度クラスタMegaProto2005

    • Author(s)
      中島浩, 中村宏, 佐藤三久, 朴泰祐, 松岡聡, 高橋大介, 堀田義彦
    • Journal Title

      情報処理学会論文誌コンピューティングシステム Vol.46, No.SIG12(ACS11)

      Pages: 46-61

    • NAID

      110002769823

    • Related Report
      2005 Annual Research Report
  • [Journal Article] ビット分割構成によるレジスタファイルのサイズおよびポート数削減手法2005

    • Author(s)
      近藤正章, 中村宏
    • Journal Title

      情報処理学会論文誌コンピューティングシステム Vol.46, No.SIG12(ACS11)

      Pages: 62-72

    • NAID

      110002769824

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Small, Fast and Low-Power Register File byBit-Partitioning2005

    • Author(s)
      M.Kondo, H.Nakamura
    • Journal Title

      Proceedings of HPCA-11

      Pages: 40-49

    • Related Report
      2004 Annual Research Report
  • [Journal Article] ソフトウェア制御オンチップメモリにおける演算処理を考慮した低消費電力化手法2005

    • Author(s)
      藤田元信, 近藤正章, 中村宏
    • Journal Title

      情報処理学会研究報告 2005-ARC-162(35) HPC-101(35)

      Pages: 205-210

    • NAID

      110002775125

    • Related Report
      2004 Annual Research Report
  • [Journal Article] ソフトウェア制御オンチップメモリ向け自動最適化コンパイラの提案2004

    • Author(s)
      藤田 元信, 近藤 正章, 中村 宏
    • Journal Title

      情報処理学会研究会論文誌 Vol.45,No.SIG1(AGS4)

      Pages: 77-87

    • NAID

      110002712436

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法2004

    • Author(s)
      藤田 元信, 田中 慎一, 近藤 正章, 中村 宏
    • Journal Title

      情報処理学会論文誌コンピューティングシステム Vol.45,NoSIG1(ACS7)

      Pages: 219-228

    • NAID

      110002712294

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Data Movement Optimization for Software-Controlled On-Chiip Memory2004

    • Author(s)
      Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
    • Journal Title

      Proc. of The 8th Workshop on Interaction between Compilers and Computer Architectures

      Pages: 120-127

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Automatic Compilation for Software-controlled On-chip Memory2004

    • Author(s)
      M.Fujita, M.Kondo, H.Nakamura
    • Journal Title

      IPSJ Transaction on Advanced Computing Systems Vol.45, No.SIG1(ACS4)

      Pages: 77-87

    • NAID

      110002712436

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] A Static Power Reduction Method for Software Controlled On-Chip Memory2004

    • Author(s)
      M.Fujita, S.Tanaka, M.Kondo, H.Nakamura
    • Journal Title

      IPSJ Transaction on Advanced Computing Systems Vol.45, No.SIG11(ACS7)

      Pages: 219-228

    • NAID

      110002712294

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Data Movement Optimization for Software-Controlled On-Chip Memory2004

    • Author(s)
      Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura
    • Journal Title

      Proc. of The 8th Workshop on Interaction between Compilers and Computer Architectures

      Pages: 120-127

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] ソフトウェア制御オンチップメモリにおけるスタティック消費電力削減手法2004

    • Author(s)
      藤田元信, 近藤正章, 中村宏
    • Journal Title

      情報処理学会論文誌 Vol.45,No.SIG11(ACS7)

      Pages: 219-228

    • NAID

      110002712294

    • Related Report
      2004 Annual Research Report
  • [Journal Article] プロセッサの消費電力測定と低消費電力プロセッサによるクラスタの検討2004

    • Author(s)
      堀田義彦, 佐藤三久, 朴泰祐, 高橋大介, 中島佳宏, 高橋睦史, 中村宏
    • Journal Title

      情報処理学会論文誌 Vol.45,No.SIG11(ACS7)

      Pages: 207-218

    • NAID

      110002712293

    • Related Report
      2004 Annual Research Report
  • [Journal Article] ビット分割によるレジスタファイル削減手法2004

    • Author(s)
      近藤正章, 中村宏
    • Journal Title

      情報処理学会研究報告 2004-ARC-159(3)

      Pages: 13-18

    • Related Report
      2004 Annual Research Report
  • [Journal Article] educing Memory System Energy by Sofware-Controlled On-Chip Memory2003

    • Author(s)
      M.Kondo, H.Nakamura
    • Journal Title

      IEICE Trans. on Electronics Vol.E86-C No.4

      Pages: 580-588

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Reducing Memory System Energy by Software-Controlled On-Chip Memory2003

    • Author(s)
      M.Kondo, H.Nakamura
    • Journal Title

      IEICE Trans. on Electronics Vol.E86-C No.4

      Pages: 580-588

    • NAID

      110003223419

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Publications] 藤田元信, 近藤正章, 中村宏: "ソフトウェア制御オンチップメモリ向け自動最適化コンパイラの提案"情報処理学会蹴会論購コンピューティングシステム. Vol.45, No.SIG1(ACS4). 77-87 (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] N.Sretasereekul, H.Saito, E.Kim, M.Ozcan, M.Imai, H.Nakamura, T.Nanya: "Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design"IEICE Trans.on Fundamentals, Special Issue on VLSI Design and CAD Algorithms. Vol.E-86-A, No.12. 3028-3037 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] H.Saito, E.Kim, M.Imai, N.Sretasereekul, H.Nakamura, T.Nanya: "Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions"Proc.of Asynch 2003. 184-195 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 藤田元信, 近藤正章, 中村宏: "アーキテクチャとコンパイラによるメモリ階層協調最適化の検討"情報処理学会研究報告. 2003-ARC-154(23). 133-138 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 近藤正章, 藤田元信, 中村宏: "演算部とデータ供給部の動的周波数変更による低消費電力化手法の検討"情報処理学会研究報告. 2003-ARC-154(17). 97-102 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 近藤正章: "ソフトウェア可制御オンチップメモリを用いた低消費電力化の検討"情報処理学会 並列処理シンポジウム予稿集. 285-288 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Masaaki Kondo: "Cache Line Impact on 3D PDE Solvers"Proc. of International Symposium on High Performance Computing, Lecture Notes in Computer Science 2327 (Springer-Verlag). No.2327. 301-309 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Taku Ohneda: "Design And Evaluation Of High Performance Microprocessor With Reconfigurable On-Chip Memory"Proc. of IEEE Asia-Pacific Conference on Circuits and Systems. 211-216 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] Hiroshi Nakamura: "Formal Verification of a Pipelined Processor with New Memory Hierarchy using a Commercial Model Checker"Proc. of IEEE Pacific Rim Dependable Computing Conference. 321-324 (2002)

    • Related Report
      2002 Annual Research Report
  • [Publications] 高橋睦史: "HPC向けオンチップメモリプロセッサアーキテクチャSCIMAのSMP化の検討と性能評価"情報処理学会ハイパフォーマンスコンピューティングと計算科学システム. 47-54 (2002)

    • Related Report
      2002 Annual Research Report

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Published: 2002-04-01   Modified: 2016-04-21  

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