Researches on hardware algorithms for arithmetic operations in finite fields.
| Project/Area Number |
14380142
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Nagoya University |
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Principal Investigator |
TAKAGI Naofumi Nagoya University, Graduate School of Information Science, Professor, 大学院・情報科学研究科, 教授 (10171422)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAGI Kazuyoshi Nagoya University, Graduate School of Information Science, Assistant Professor, 大学院・情報科学研究科, 講師 (70273844)
NAKAMURA Kazuhiro Nagoya University, Graduate School of Information Science, Assistant Professor, 大学院・情報科学研究科, 助手 (90335076)
NISHINAGA Nozomu National Institute of Information and Communication Technology, Wireless Communications Laboratory, Researcher, 無線通信部門, 研究員
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥14,500,000 (Direct Cost: ¥14,500,000)
Fiscal Year 2004: ¥4,200,000 (Direct Cost: ¥4,200,000)
Fiscal Year 2003: ¥5,800,000 (Direct Cost: ¥5,800,000)
Fiscal Year 2002: ¥4,500,000 (Direct Cost: ¥4,500,000)
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| Keywords | finite field arithmetic / modular arithmetic / integer Division / modular reduction / cryptosystem / hardware algorithm / VLSI / 乗算剰余算 / 剰余系除算 / 有限体上の除算 / 暗号化・復号 |
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| Research Abstract |
We have investigated hardware algorithms for arithmetic operations in finite fields which play important roles in cryptosystems as well as in coding systems, and have obtained the following results.
(1)We improved the hardware algorithm for division in finite field GF(2^m) based on the extended binary GCD method that we proposed previously, designed a circuit based on it, and evaluated the circuit by computer simulation as well as fabrication of a prototype LSI.
(2)We developed a hardware algorithm for modular division/Montgomery multiplication, designed a circuit based on it, and evaluated the circuit by computer simulation. The modular division, i.e., division in finite field GF(p), is based on the extended binary GCD method. The two operations can be performed using a circuit whose amount of hardware is about the same as that of a modular divider based on the extended binary GCD method.
(3)We developed a hardware algorithm for modular division/modular multiplication/Montgomery multipli
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cation, designed a circuit based on it, and evaluated the circuit by computer simulation. The modular division is based on the extended Euclid's algorithm. The three operations can be performed using a circuit whose amount of hardware is about the same as that of a modular divider based on the extended Euclid's algorithm.
(4)We developed a hardware algorithm for computing multiplicative inverse in finite field GF(2^m) based on the extended Euclid's algorithm. This algorithm executes several steps of the extended Euclid's algorithm in one step using a look-up table. This algorithm is also suited for software implementation.
(5)We developed a hardware algorithm for integer division which is used for modular reduction. In modular arithmetic, i.e., arithmetic in GF(p), modular reduction by p, i.e., the residue calculation of an integer divided by the modulus p, often appears. Since integer division is widely used, it is attractive to embed an integer divider based on the proposed algorithm in microprocessors for accelerating various computations. Less
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Report
(4 results)
Research Products
(20 results)
