| Project/Area Number |
14380146
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Kyusyu Institute of Technology |
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Principal Investigator |
SASAO Tsutomu Kyusyu Institute of Technology, Faculty of Computer Science and Systems Engineering, Professor, 情報工学部, 教授 (20112013)
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| Co-Investigator(Kenkyū-buntansha) |
KAJIHARA Seiji Kyusyu Institute of Technology, Faculty of Computer Science and Systems Engineering, Professor, 情報工学部, 教授 (80252592)
IGUCHI Yukihiro Meiji University, School of Science and Technology, Associate Professor, 理工学部, 助教授 (60201307)
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥8,700,000 (Direct Cost: ¥8,700,000)
Fiscal Year 2004: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2003: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2002: ¥4,300,000 (Direct Cost: ¥4,300,000)
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| Keywords | FPGA / Memory / Reconfigurable logic / Binary decision diagram / functional decomposition / Logic design / 再構成可能論理 / 再構成可能倫理 |
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| Research Abstract |
RAMs(Random Access Memory) and PLAs(Programmable-Logic-Array) are popular PLDs(programmable logic devices) that realize multiple-output combinational logic functions. However, when the number of inputs and/or outputs for the target function is large, these devices often require excessive amount of hardware. The main results of the research are as follows :
1.Development of architecture.
We developed two types of architecture that realizes multiple-output functions. An LUT cascade is a serial connection of LUTs(Look-up tables), and realize a combinational circuit. It is easy to design and layout. An LUT ring emulates an LUT cascade, and realize both a combinational and a sequential circuit. It consists of the memory for logic, the programmable interconnection network, and the control circuit. The LUT cascade is faster, but has alimited logic capability. The LUT cascade uses relatively large LUTs (10 to 15 inputs), and the interconnections between LUTs are limited to the adjacent cells in
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the cascade. On the other hand, the LUT ring is slower, but has a higher logic capability. LUT cascades and LUT rings can be directly generated from the BDDs for the target functions. Their performance is easy to estimate.
2.Development of synthesis method for multiple-output logic functions.
We developed a decomposition method for incompletely specified multiple-output function using BDD(binary decision diagram).With this method, we can design a LUT cascade with intermediate outputs. We designed radix converters and arithmetic circuits, and showed that our method reduced the amount of hardware by 20 to 30 percents, compared with the methods that do not consider don't cares.
3.Development of method to reduce the number of rail outputs.
We developed a method to reduce the number of rail outputs for an LUT cascade with intermediate outputs by considering encoding. Reduction of the number of outputs of LUTs reduces the amount of memory. Experimental results show that our approach reduces the number of outputs of LUTs by 10%.
4.Development of memory packing algorithm.
In LUT ring, we can reduce the size of memory by using memory packing. We applied this method to various functions, and confirmed that we can reduce the amount of memory by 40 percents. Less
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