| Project/Area Number |
14580396
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
計算機科学
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| Research Institution | Osaka Institute of Technology |
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Principal Investigator |
KUTSUWA Toshiro Osaka Institute of Technology, Faculty of Engineering, Professor, 工学部, 教授 (00079584)
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| Co-Investigator(Kenkyū-buntansha) |
HARASHIMA Katsumi Osaka Institute of Technology, Faculty of Engineering, Associate Professor, 工学部, 助教授 (20238174)
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| Project Period (FY) |
2002 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 2004: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2003: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2002: ¥1,400,000 (Direct Cost: ¥1,400,000)
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| Keywords | Voice Communication / Hardware Design / Design Automation / Hardware Description Language / FPGA Design / Voice Recognition / Voice Input / Voice Recognition Application Program |
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| Research Abstract |
It is mankind's eternal wish that every- thing can be made automatically by speaking to the computer. But in the case of the schematic input, it is very difficult to design the hardware by means of voice communication. Recently, according to the development of hardware description language and voice recognition software, hardware design may be able to be performed easily by voice communication. Then we develop a Voice Recognition Application Program (VRAP) and a graphical user interface (GUI) to develop easily the hardware design system of VHDL by means of voice communication. Furthermore, we adopt a reverse description method for the effective design and propose the effective design method for combinational circuit and sequential circuit.
On the combinational circuit design, we have developed an application program VRCD_C (Voice Recognition Circuit Design of Combinational Logic), which prodeces automatically HDL description from the truth table made by voice input. For the sequential circuit, we have also developed VRCD_S (Voice Recognition Circuit Design of Sequential Logic), which produces HDL from transition table made by voice input. Forthermore, we have been trying now large scale circuit design by appling the VRCD_C,VRCD_S and system description language.
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