Grant-in-Aid for Scientific Research (S)
|Allocation Type||Single-year Grants |
|Research Institution||Hiroshima University |
IWATA Atsushi Hiroshima University, Graduate School of Advanced Sciences of Matter, Professor (30263734)
MATTAUSH Hans juregen Hiroshima University, Research Center for Nanodevices and Systems, Professor (20291487)
MIURA Mitiko Hiroshima University, Graduate School of Advanced Sciences of Matter, professor (70291482)
SASAKI Mamoru Hiroshima University, Graduate School of Advanced Sciences of Matter, Associate Professor (70235274)
KOIDE Tetsushi Hiroshima University, Research Center for Nanodevices and Systems, Associate Professor (30243596)
上野 弘明 広島大学, 大学院・先端物質科学研究科, 助手 (50314729)
|Project Period (FY)
2003 – 2007
Completed (Fiscal Year 2007)
|Budget Amount *help
¥111,930,000 (Direct Cost: ¥86,100,000、Indirect Cost: ¥25,830,000)
Fiscal Year 2007: ¥21,580,000 (Direct Cost: ¥16,600,000、Indirect Cost: ¥4,980,000)
Fiscal Year 2006: ¥21,580,000 (Direct Cost: ¥16,600,000、Indirect Cost: ¥4,980,000)
Fiscal Year 2005: ¥22,750,000 (Direct Cost: ¥17,500,000、Indirect Cost: ¥5,250,000)
Fiscal Year 2004: ¥21,710,000 (Direct Cost: ¥16,700,000、Indirect Cost: ¥5,010,000)
Fiscal Year 2003: ¥24,310,000 (Direct Cost: ¥18,700,000、Indirect Cost: ¥5,610,000)
|Keywords||wireless interconnection / inductor coupling / three dimensional integration / recognition systems / associative memory / pattern matching / learning function / 集積化インダクタ / マルチチップビジョン / 連想メモリベース画像処理 / 物体認識 / 三次元集積システム / 無線インタコネクション / スパイラルインダクタ / ビジョンチップ / オブジェクト認識 / 三次元集積技術 / MOSトランジスタモデル / PWM信号 / チップ間無線通信 / FDTD法 / 回路設計 / 3次元磁界解析 / CMOSテクノロジー|
3D integration technologies using wireless interconnections and object recognition systems Research achievements:
(1). Chip-to-chip wireless interconnection and 3D integration devices
chip-to-chip wireless interconnection using electromagnetic induction between coupled inductors was proposed, and test circuits were designed and fabricated. Bit rate of 1Gb/s was achieved with 1mW power dissipation; Bit rate of 2.4Gb/s was achieved with high speed design.
Three dimensional integration technology utilizing wireless interconnection using on-chip antenna and inductor coupled interconnection, named 3DCSS was proposed. Basic scheme and prototype systems were designed and fabricated. High performance image processing was realized with 3DCSS.
Standing wave oscillator using inductor termination and coupling was proposed and a test chip was designed and fabricated with an 0.18um CMOS technology. 10GHz high quality oscillation signal with low phase noise was obtained.
MOS device mod
el (HiSIM) using surface potential was proposed, and highly accurate description capability with small number of parameters was effective for larger than 10GHz frequency range RF circuit applications.
(2) Highly cognitive systems using chip-to-chip wireless interconnection
An associative memory using analog and digital combined circuit techniques was developed, and highly speed operation with low power dissipation were confirmed. Highly functional, high performance pattern matching which was essential for detection, tracking and recognition of objects in image signals was implemented utilizing the associative memories.
3D prototype system integrating three kinds of image processing chips was implemented, and expected data transfer speed was obtained. Low voltage operated low noise amplifier and high performance VCO were also developed for basic circuit blocks.
(3) Processing algorithm for implementing brain functions and systems
Learning algorithm based on a human brain was implemented in an associative memory. By using the algorithm, a memory based learning model was proposed and its effectiveness for image recognition was confirmed. Less