| Project/Area Number |
15206039
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (A)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Electron device/Electronic equipment
|
|---|
| Research Institution | Tokyo Institute of Technology |
|---|
Principal Investigator |
SAKAI Tetsushi Tokyo Institute of Technology, Interdisciplinary Graduate School of Science and Technology, Professor, 大学院・総合理工学研究科, 教授 (60313368)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
OHMI Shun-ichiro Tokyo Institute of Technology, Interdisciplinary Graduate School of Science and Technology, Associate Professor, 大学院・総合理工学研究科, 助教授 (30282859)
MUROTA Junichi Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (70182144)
|
|---|
| Project Period (FY) |
2003 – 2004
|
| Project Status |
Completed (Fiscal Year 2004)
|
| Budget Amount *help |
¥51,480,000 (Direct Cost: ¥39,600,000、Indirect Cost: ¥11,880,000)
Fiscal Year 2004: ¥8,060,000 (Direct Cost: ¥6,200,000、Indirect Cost: ¥1,860,000)
Fiscal Year 2003: ¥43,420,000 (Direct Cost: ¥33,400,000、Indirect Cost: ¥10,020,000)
|
|---|
| Keywords | MOSFET / SiGe / ML-MOSFET / TML-MOSFET / SBSI / hydoro-nitric acid / lateral selective etching of SiGe / HfNO / ML-MOSFET / フッ硝酸溶液 / i-SiGe横方向選択エッチング / HfON / PtSi |
|---|
| Research Abstract |
The summary of this project is as follows
1) The electrical characteristics of the proposed Multi-Layer Channel MOSFET (ML-MOSFET) were investigated by the 3D simulation. A new process for ML-MOSFET based on the bulk wafer was proposed. This process contains more self-align steps and it was suitable for ultra-small geometry device with higher device spec and cost performance.
2) The vertical etching process for Si/SiGe/Si stacked layers by ICP dry etching system, which was introduced by this fund, and lateral selective etching process of SiGe layers by the etchant of HF/HNO_3/H_2O were investigated.
3) The TML-MOSFET (Twin-Multi-Layer MOSFET) with twice of higher drive current compared to the conventional ML-MOSFET was proposed based on the results of (1) and (2) mentioned above. The fabrication process of TML-MOSFET was also proposed, which contains more self-align steps and it is suitable for ultra-small geometry device.
4) The HfON gate insulator formed by the ECR plasma nitridation of
… More
HfO_2 was investigated. The film annealed at 1000℃ in N_2 ambient by the RTA was found to be suitable for MOSFET applications.
5) Novel SOI Technology SBSI (Separation by Bonding Silicon Islands) was proposed. SBSI enables the ultra-thin SOI/BOX layers, multi-layer SOI, and partial SOI wafer with simultaneous SOI and isolation formations initiating from bulk Si wafers. SBSI would have a significant impact on the semiconductor industry so that further experiments were carried out and basic patent was applied for Japan and foreign countries.
6) Several basic process steps for SBSI, such as lateral selective etching of SiGe layers of Si/SiGe/Si structures by the etchant of HF/HNO_3/H_2O, bonding Si islands by high temperature annealing and/or oxidation. From the results of (6) mentioned above, SOI with simultaneous isolation was fabricated by SBSI on 2 inch wafers. The 40 nm-thick SOI with 29 nm-thick BOX layers were formed and good breakdown voltage of isolation, such as 15 V or higher, was obtained. The excellent crystallinity of SOI layer was confirmed by the cross-sectional TEM image. These results suggested that the SBSI would be the promising SOI technology for future ultra-small geometry CMOS/SOI with excellent characteristics.
7) Based on the results mentioned above, cooperative research with company has been started since 2004 for the contribution to the industry and realization of the SBSI. Less
|
