| Project/Area Number |
15206042
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | KYUSHU UNIVERSITY (2004-2005)
The University of Tokyo (2003) |
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Principal Investigator |
HATTORI Reiji Kyushu University, Graduate School of Information Science and Electrical Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (60221503)
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| Co-Investigator(Kenkyū-buntansha) |
IKEDA Akihiro Kyushu University, Graduate School of Information Science and Electrical Engineering, Research Associate, 大学院・システム情報科学研究院, 助手 (60315124)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥49,790,000 (Direct Cost: ¥38,300,000、Indirect Cost: ¥11,490,000)
Fiscal Year 2005: ¥9,750,000 (Direct Cost: ¥7,500,000、Indirect Cost: ¥2,250,000)
Fiscal Year 2004: ¥11,700,000 (Direct Cost: ¥9,000,000、Indirect Cost: ¥2,700,000)
Fiscal Year 2003: ¥28,340,000 (Direct Cost: ¥21,800,000、Indirect Cost: ¥6,540,000)
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| Keywords | Plastic substrate / Planarization / Burying / Electronic paper / flat panel display |
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| Research Abstract |
1.We have established the process to bury the LSI chip with 20 mm×2mm in dimension into the plastic substrate (Polycarbonate) with 0.5 mm in thickness. After burying the LSI chip, we confirmed the flatness of the surface between the chip and substrate, which has no problem to wiring on them. We have also developed the process to deposit the insulator of SiO2 layer by spin coating
2.The contact via was formed by RIE etching with the new apparatus (SAMCO Int.Co.) we purchased newly in this project. There are few works to make the via on a plastic substrate and we had to optimized in precisely the conditions for etching rate, the side-wall sharpness, the bottom surface flatness, and so on.
3.The ITO depositing process after forming the insulator on the chip and plastic substrate also optimized. We had a problem of the high temperature process during the depositing the ITO on the plastic substrate because the plastic substrate cannot be ensured the high temperature more than 200℃, but we optimized the depositing conditions for ITO at room-temperature and got a good quality. ITO layer. We also had a problem that the plastic substrate surface changed to whiten, but this problem also solved by choosing the suitable etching solvent and the temperature.
4.We have designed and fabricated a custom LSI and estimated it. This LSI was for driving the electronic paper, which has 160 outputs, 3 output levels (including grand level), and the current sinkable function on a middle level. This was available for column and row drivers.
5.We connected this LSI to the quick-response liquid powder display (QR-LPD) and evaluated the image quality. In order to operate this driver, we had to make the circuit for micro computer, power sources, latch IC, and connectors. Using our custom LSI, the image quality of QR-LPD was much improved because of the three-level output.
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