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Research on an efficient analysis method of real-time software based on a level oriented net model

Research Project

Project/Area Number 15300009
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Software
Research InstitutionNational Institute of Informatics

Principal Investigator

YONEDA Tomohiro  National Institute of Informatics, Infrastructure Systems Research Division, Professor, 情報基盤研究系, 教授 (30182851)

Project Period (FY) 2003 – 2004
Project Status Completed (Fiscal Year 2004)
Budget Amount *help
¥7,900,000 (Direct Cost: ¥7,900,000)
Fiscal Year 2004: ¥5,700,000 (Direct Cost: ¥5,700,000)
Fiscal Year 2003: ¥2,200,000 (Direct Cost: ¥2,200,000)
KeywordsLevel Time Petri net / Partial order reduction / Hierarchical verification / Real time software / Timed automaton / 形式的検証 / レベルタイムペトリネット
Research Abstract

It is well known that a timed automaton is a formal model for real-time systems which is level oriented and has rich expressiveness. Our experience, however, has found that its generality comes at an increase in analysis complexity, and this increased generality is not always necessary for verifying some class of real-time, systems. Thus, this work has tackled the challenge to develop an efficient tool based on a simpler model with still sufficient expressiveness.
In the first step of this work, a new formal model has been obtained by extending the time Petri net model with preserving the simplicity of its analysis. In this new model called LTN (Level Time Petri net), firing an LTN transition can assign values to a set of boolean variables, and the validity of an expression over the boolean variables is also used as an enabling condition of an LTN transition in addition to the marking. Next, its efficient analysis procedure based on the partial order reduction has been developed and an prototype for it has been implemented. This algorithm also has an ability of verifying systems hierarchically, which sometimes reduces the average complexity of the verification of large systems. To demonstrate this ability, a little large case study for verifying the instruction cache mechanism of TITAC 2 asynchronous microprocessor has been done. Through the case study, the hierarchical verification technique has been evaluated. Finally, we have designed a graphical user interface (GUI) for especially supporting the hierarchical verification steps, and a verification tool VINAS-P(Ver.2) with it has been developed.

Report

(3 results)
  • 2004 Annual Research Report   Final Research Report Summary
  • 2003 Annual Research Report
  • Research Products

    (8 results)

All 2003 Other

All Journal Article (7 results) Publications (1 results)

  • [Journal Article] Partial Order Reduction for Timed Circuit Verification Based on a Level Oriented Model2003

    • Author(s)
      Tomoya Kitai
    • Journal Title

      電子情報通信学会英文論文誌 Vol.E86-D

      Pages: 2601-2611

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Partial Order Reduction for Timed Circuit Verification Based on a Level Oriented Model2003

    • Author(s)
      Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris Myers
    • Journal Title

      Proc. of IEICE Vol.E86-D No.12

      Pages: 2601-2611

    • NAID

      10012560062

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Partial order Reduction for Detecting Safety and Timing Failures of Timed Circuits

    • Author(s)
      Denduang Pradubsuwun
    • Journal Title

      電子情報通信学会英文論文誌 (印刷中)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Failure Trace analysis of Timed Circuits for Automatic Timing Constraints Derivation

    • Author(s)
      Tomoya Kitai
    • Journal Title

      電子情報通信学会英文論文誌 (印刷中)

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

    • Author(s)
      Denduang Pradubsuwun, Tomohiro Yoneda, Chris Myers
    • Journal Title

      Proc. of IEICE (to appear)

    • NAID

      110003173584

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Failure Trace analysis of Timed Circuits for Automatic Timing Constraints Derivation

    • Author(s)
      Tomoya Kitai, Tomohiro Yoneda, Chris Myers
    • Journal Title

      Proc. of IEICE (to appear)

    • NAID

      110003502000

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits

    • Author(s)
      Denduang Pradubsuwun, Tomohiro Yoneda, Chris Myers
    • Journal Title

      電子情報通信学会英文論文誌 (採録決定済み)

    • NAID

      110003173584

    • Related Report
      2004 Annual Research Report
  • [Publications] Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris Myers: "Partial Order Reduction for Timed Circuit Verification Based on a Level Oriented Model"電子情報通信学会英文論文誌. E86D・12. 2601-2611 (2003)

    • Related Report
      2003 Annual Research Report

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Published: 2003-04-01   Modified: 2016-04-21  

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