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Research on high speed packet management with Reconfigurable Hardware

Research Project

Project/Area Number 15300013
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionUniversity of Tsukuba

Principal Investigator

YAMAGUCHI Yoshinori  University of Tsukuba, Graduate School of Systems and Information Engineering, Professor, 大学院システム情報工学研究科, 教授 (00312827)

Co-Investigator(Kenkyū-buntansha) MAEDA Atsushi  University of Tsukuba, Graduate School of Systems and Information Engineering, Associate Professor, 大学院システム情報工学研究科, 助教授 (50293139)
TODA Kenji  AIST, Information Technology Research Institute, Senior Researcher, 情報技術研究部門, 主任研究員 (70357565)
佐谷野 健二  産業技術総合研究所, 情報処理研究部, 研究員
Project Period (FY) 2003 – 2006
Project Status Completed (Fiscal Year 2006)
Budget Amount *help
¥12,300,000 (Direct Cost: ¥12,300,000)
Fiscal Year 2006: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2005: ¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2004: ¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2003: ¥3,300,000 (Direct Cost: ¥3,300,000)
KeywordsSecure network / Intrusion detection system / FPGA / Nondeterministic Finite Automaton / encryption system / IDS / NFA / DFA / 侵入検地システム / パケット
Research Abstract

Attendant upon the acceleration of network, it is said to be difficult to develop network equipment which has the processing efficiency corresponding the speed of the network. In this research, we are going to develop network equipments which can accelerate the processing speed by using the rewritable semiconductor devices, such as FPGA.
As the first topic, research and development of the network IDS ( Intrusion Detection System) is studied, especially the efficient execution scheme of the system using FPGA devices is pursued. The system firstly forms the finite-state machine from IDS patterns, next it is converted to hardware description language automatically. The research themes for this topic are to develop the efficient execution processing scheme based on the FPGA devices with regarding the reduction of the hardware quantity. Finally, IDS experimental system which exceeds 10Gbps was made, by using the IDS pattern matching circuit based on the nondeterministic finite automaton (NFA). On this system the reduction of the circuit scale of FPGA is also realized. Furthermore, in order to do the further reduction of the hardware quantity of the FPGA circuit, more research is pursued by adopting a data compression technique to the circuit design.
As the second topic, we propose the reconfigurable system model which use FPGA to encrypt the data in the server-client encryption communication. In such a system, raising the availability of FPGA improves the performance. Therefore, it is important that the development of the prediction method to reducing useless reconfiguration of FPGA effectively. We propose the method of predicting the encryption algorithm used in the near future requests based on history of requests received so far to improve the efficiency of encryption. We employ the generalized n-gram model for that prediction, and verify its characteristics.

Report

(5 results)
  • 2006 Annual Research Report   Final Research Report Summary
  • 2005 Annual Research Report
  • 2004 Annual Research Report
  • 2003 Annual Research Report
  • Research Products

    (26 results)

All 2007 2006 2005 2004 Other

All Journal Article (22 results) Patent(Industrial Property Rights) (2 results) Publications (2 results)

  • [Journal Article] 暗号通信パケットストリームのn-gram 予測によるFPGA動的再構成手法とその評価2007

    • Author(s)
      丹羽雄平, 前田敦司, 山口喜教
    • Journal Title

      情報処理学会論文誌 : コンピューティングシステム Vol.48,No.SIG 3 (ACS17)

      Pages: 27-44

    • NAID

      110006207848

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A method of reducing reconfiguration overhead of an FPGA-based encryption communication system by predicting the use of encryption algorithm2007

    • Author(s)
      Niwa Y., Maeda, A., Yamaguchi, Y.
    • Journal Title

      IPSJ Transactions on Advanced Computing Systems Vol.48, No.SIG3(ACS17)

      Pages: 27-44

    • NAID

      110002769828

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 暗号通信パケットストリームのn-gram予測によるFPGA動的再構成手法とその評価2007

    • Author(s)
      丹羽雄平, 前田敦司, 山口喜教
    • Journal Title

      情報処理学会論文誌 : コンピューティングシステム 48・SIG3(ACS17)

      Pages: 27-44

    • NAID

      110006207848

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Highly Efficient String Matching Circuit for IDS with FPGA2006

    • Author(s)
      Katashita, T., Maeda, A., Toda, K., Yamaguchi, Y.
    • Journal Title

      Proc. 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06)

      Pages: 285-286

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Highly Efficient String Matching Circuit for IDS with FPGA,.2006

    • Author(s)
      Katashita, T., Maeda, A., Toda, K., Yamaguchi, Y.
    • Journal Title

      Proc.14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06)

      Pages: 285-286

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Highly Efficient String Matching Circuit for IDS with FPGA2006

    • Author(s)
      Katashita, T., Maeda, A., Toda, K., Yamaguchi,Y
    • Journal Title

      Proc.14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'06)

      Pages: 285-286

    • Related Report
      2006 Annual Research Report
  • [Journal Article] A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection2006

    • Author(s)
      Katashita, T., Maeda, A., Toda, K., Yamaguchi,Y
    • Journal Title

      16th International Conference on Field Programmable Logic and Applications (poster)

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Dynamic load balancing for the reduction of network traffic using network transferable computer2006

    • Author(s)
      久行恵美, 井上伸二, 角田良明, 戸田賢二, 須崎有康
    • Journal Title

      電子情報通信学会論文誌B vol.J89-B,no.4

      Pages: 443-453

    • NAID

      210000183172

    • Related Report
      2006 Annual Research Report
  • [Journal Article] 余剰FFと位相シフトクロックを利用したFPGA回路の低消費電力実装手法2005

    • Author(s)
      片下敏宏, 前田敦司, 山口喜教
    • Journal Title

      電子情報通信学会論文誌 Vol.J88-D1 No.7

      Pages: 1132-1142

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 暗号通信におけるリクエスト予測を用いたFPGA再構成オーバヘッドの低減手法2005

    • Author(s)
      丹羽雄平, 前田敦司, 山口喜教
    • Journal Title

      情報処理学会論文誌 : コンピューティングシステム Vol.46,No.SIG12(ACS11)

      Pages: 110-119

    • NAID

      110002769828

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] FPGAによる高速かつ軽量なNFAパターンマッチング回路2005

    • Author(s)
      片下敏宏, 前田敦司, 小野正人, 戸田賢二, 山口喜教
    • Journal Title

      情報処理学会論文誌 : コンピューティングシステム Vol.46,No.SIG12(ACS11)

      Pages: 120-128

    • NAID

      110002769829

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A low power design method for FPGA using extra flip-flops drivers by phase shift clock (in Japanese)2005

    • Author(s)
      Katashita, T., Maeda, A., Sayano, K., Yamaguchi, Y.
    • Journal Title

      IEICE Trans. Vol.J88-D1 No.7

      Pages: 1132-1142

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A method of reducing reconfiguration overhead of an FPGA-based encryption communication system by predicting the use of encryption algorithm.2005

    • Author(s)
      Niwa Y., Maeda, A., Yamaguchi, Y.
    • Journal Title

      IPSJ Transactions on Advanced Computing Systems Vol.46, No.SIG12(ACS11)

      Pages: 110-119

    • NAID

      110002769828

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Fast and compact NFA pattern matching circuit using FPGAs2005

    • Author(s)
      Katashita, T., Maeda, A., Ono, M.Toda, K., Yamaguchi, Y.
    • Journal Title

      IPSJ Transactions on Advanced Computing Systems Vol.46, No.SIG12(ACS11)

      Pages: 120-128

    • NAID

      110002769829

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 余剰FFと位相シフトクロックを利用したFPGA回路の低消費電力実装手法2005

    • Author(s)
      片下敏宏, 前田敦司, 山口喜教
    • Journal Title

      電子情報通信学会論文誌 J88-D1・7

      Pages: 1132-1142

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 暗号通信におけるリクエスト予測を用いたFPGA再構成オーバヘッドの低減手法2005

    • Author(s)
      丹羽雄平, 前田敦司, 山口喜教
    • Journal Title

      情報処理学会論文誌:コンピューティングシステム 46・SIG12(ACS11)

      Pages: 110-119

    • NAID

      110002769828

    • Related Report
      2005 Annual Research Report
  • [Journal Article] FPGAによる高速かつ軽量なNFAパターンマッチング回路2005

    • Author(s)
      片下敏宏, 前田敦司, 小野正人, 戸田賢二, 山口喜教
    • Journal Title

      情報処理学会論文誌:コンピューティングシステム 46・SIG12(ACS11)

      Pages: 120-128

    • NAID

      110002769829

    • Related Report
      2005 Annual Research Report
  • [Journal Article] FPGA-Based Content Protection System for Embedded Consumer Electronics2005

    • Author(s)
      Yokoyama, H., Toda, K
    • Journal Title

      Proc. The 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005)

      Pages: 502-507

    • NAID

      110003206378

    • Related Report
      2005 Annual Research Report
  • [Journal Article] A low power AES circuit design for FPGA implementation2004

    • Author(s)
      Katashita, T., Maeda, A., Sayano, K., Yamaguchi, Y.
    • Journal Title

      Proc. COOL Chips VII

      Pages: 59-67

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A low power AES circuit design for FPGA implementation,2004

    • Author(s)
      Katashita, T., Maeda, A., Sayano, K., Yamaguchi, Y.
    • Journal Title

      Proc.COOL Chips VII

      Pages: 59-67

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A low power AES circuit design for FPGA implementation2004

    • Author(s)
      T.Katashita, A.Maeda, K.Sayano, Y.Yamaguchi
    • Journal Title

      Proc.COOL Chips VII Vol.1

      Pages: 59-67

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 余剰FFと位相シフトクロックを利用したFPGA回路の低消費電力実装手法

    • Author(s)
      片下敏宏, 前田敦司, 山口喜教
    • Journal Title

      電子情報通信学会論文誌 (発表予定)

    • Related Report
      2004 Annual Research Report
  • [Patent(Industrial Property Rights)] パターンマッチング装置(その形成方法、それを用いたネットワーク不正侵入検知装置の動作方法、およびそれを用いた侵入防止システムの動作方法)2005

    • Inventor(s)
      山口喜教, 片下敏宏, 前田敦司, 戸田賢二
    • Industrial Property Rights Holder
      国立大学法人筑波大学, 独立行政法人産業技術総合研究所
    • Filing Date
      2005-11-17
    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Patent(Industrial Property Rights)] パターンマッチング装置、その形成方法、それを用いたネットワーク不正侵入検知装置の動作方法、およびそれを用いた侵入防止システムの動作方法2005

    • Inventor(s)
      山口 喜教, 前田 敦司, 片下 敏宏, 戸田 賢二
    • Industrial Property Rights Holder
      筑波大学, 産業技術総合研究所
    • Industrial Property Number
      2005-333199
    • Filing Date
      2005-11-17
    • Related Report
      2005 Annual Research Report
  • [Publications] 前田敦司, 山口喜教: "Schemeインタプリタにおける仮想マシンアーキテクチャの最適化"情報処理学会論文誌:プログラミング. 44,No.SIG 13(PRO 18). 47-57 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] T.Katashita, A.Maeda, K.Sayano, Y.Yamaguchi: "A low power AES circuit design for FPGA implementation"Proc.COOL Chips VII. (in press). (2004)

    • Related Report
      2003 Annual Research Report

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Published: 2003-04-01   Modified: 2016-04-21  

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