| Project/Area Number |
15300014
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | The University of Tokyo |
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Principal Investigator |
INABA Mary University of Tokyo, Graduate School of Information Science and Technology, Associate Professor, 大学院・情報理工学系研究科, 特任助教授 (60282711)
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| Co-Investigator(Kenkyū-buntansha) |
IMAI Hiroshi University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院・情報理工学系研究科, 教授 (80183010)
HIRAKI Kei University of Tokyo, Graduate School of Information Science and Technology, Professor, 大学院・情報理工学系研究科, 教授 (20238348)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥15,900,000 (Direct Cost: ¥15,900,000)
Fiscal Year 2005: ¥4,100,000 (Direct Cost: ¥4,100,000)
Fiscal Year 2004: ¥5,200,000 (Direct Cost: ¥5,200,000)
Fiscal Year 2003: ¥6,600,000 (Direct Cost: ¥6,600,000)
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| Keywords | Network / Network Security / Long Fat Pipe Network / TCP / IP / IPv6 / Data Transffer / Compiler / WANPHY / Long Fat Pipe Network / AIMDアルゴリズム / Webグラフ / データインテンシィブ通信 / ウインドウコントロール / iSCSI / 並列ストリーム / ファイル共有 / グリット |
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| Research Abstract |
The objective of our project "Wide Area Infrastructure for Data Intensive Computation with application transparency", is to propose a general, non-project-specific, high-speed data transfer facility and high-speed computation facility to support data intensive scientific research projects, spread in distant locations but connected each other by high-speed backbone networks.
(1)It is well known that efficient data transfer on Long Fat Pipe Network (LFN) is quite difficult. We attained more than 90% network usage on 30,000km distance real network, on both memory to memory single stream TCP/IP data transfer and disks to disks multi stream TCP/IP data transfer, which are world record.
(2)We propose and implement Middle Hardware-Box, which is FPGA programmable with a pair of 10Gbps Ethernet port. On it, we implement FPGA functions such as packet generator, packet logger, and pseudo-LFN environment generator.
(3)We propose and implement SBT algorithm for FPGA, which executes string matching 10Gbps wire-rate speed, which can support TCP/IP context switch properly.
(4)We propose self-congestion control mechanism for maultiple streams of one system.
(5)We propose Flat-C compiler for super computing acceleration system.
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