| Project/Area Number |
15300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Osaka University |
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Principal Investigator |
HIGASHINO Teruo Osaka University, Graduate School of Information Science and Technology, Professor, 大学院・情報科学研究科, 教授 (80173144)
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| Co-Investigator(Kenkyū-buntansha) |
YASUMOTO Keiichi Nara Institute of Science and Technology, Graduate School of Information Science and Technology, Associate Professor, 情報科学研究科, 助教授 (40273396)
NAKATA Akio Osaka University, Graduate School of Information Science and Technology, Associate Professor, 大学院・情報科学研究科, 助教授 (60295839)
UMEDU Takaaki Osaka University, Graduate School of Information Science and Technology, Assistant Professor, 大学院・情報科学研究科, 助手 (10346174)
舩曳 信生 岡山大学, 工学部, 教授 (70263225)
安倍 広多 大阪市立大学, 学術情報総合センター, 講師 (40291603)
山口 弘純 大阪大学, 大学院・情報科学研究科, 助手 (80314409)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥6,600,000 (Direct Cost: ¥6,600,000)
Fiscal Year 2005: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2004: ¥1,900,000 (Direct Cost: ¥1,900,000)
Fiscal Year 2003: ¥3,200,000 (Direct Cost: ¥3,200,000)
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| Keywords | Network Systems / HW / SW Co-design / Concurrent Systems / Reliability / Parametric Model Checking / Hardware Synthesis / Linear Programming / SWコ・デザイン / リアルタイムシステム / オンチップCPU / 時間制約 / スケジューリング / 性能解析 / 実時間制約 / 実時間システム / モデル検査 |
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| Research Abstract |
Due to the progress of the high-speed wireless network technologies such as WLAN and WCDMA, many new functions like web browsing, high-quality audio playback, digital camera, and video telephony have been integrated into cellular phone terminals. Various components including CPU,DSP, memory and CCD are used to realize such highly functional terminals. In order to shorten the development period and save the total cost of components satisfying expected performance and timing constraints, we need methods for efficiently developing a real-time embedded system using general components. In this paper, we propose a method for designing high-reliable real-time embedded systems with FPGA and general hardware components. In our method, we specify a system as a parallel composition of concurrent periodic EFSMs with timing constraints. We give performance values like data processing time and data input/output time as parameters of transition conditions in the EFSMs. Using a parametric model checking technique, we derive a parameter condition C which must hold for a system specification S to proceed without deadlocks and satisfy given timing constraints R. By preparing a list of cost-performance characteristics of available components and substituting their values to the derived parameter condition C we can automatically select an appropriate combination of components which minimizes the total cost. We have developed a design support tool based on the proposed technique. From a system specification, our synthesis tool can derive an RT-level VHDL description which can be synthesized as an FPGA circuit for controlling the components and transferring data among them. We have applied our technique to development of a basic functionality of a cellular phone and confirmed its usefulness.
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