| Project/Area Number |
15300018
|
|---|
| Research Category |
Grant-in-Aid for Scientific Research (B)
|
| Allocation Type | Single-year Grants |
|---|
| Section | 一般 |
|---|
| Research Field |
Computer system/Network
|
|---|
| Research Institution | NARA INSTITUTE OF SCIENCE AND TECHNOLOGY |
|---|
Principal Investigator |
FUJIWARA Hideo NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, GRAD. SCHOOL OF INFORMATION SCINCE, PROFESSOR, 情報科学研究科, 教授 (70029346)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
INOUE Michiko NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, GRAD. SCHOOL OF INFORMATION SCINCE, ASSOCIATE PROFESSOR, 情報科学研究科, 助教授 (30273840)
OHTAKE Satoshi NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, GRAD. SCHOOL OF INFORMATION SCINCE, ASSISTANT PROFESSOR, 情報科学研究科, 助手 (20314528)
YONEDA Tomokazu NARA INSTITUTE OF SCIENCE AND TECHNOLOGY, GRAD. SCHOOL OF INFORMATION SCINCE, ASSISTANT PROFESSOR, 情報科学研究科, 助手 (20359871)
|
|---|
| Project Period (FY) |
2003 – 2006
|
| Project Status |
Completed (Fiscal Year 2006)
|
| Budget Amount *help |
¥15,200,000 (Direct Cost: ¥15,200,000)
Fiscal Year 2006: ¥2,800,000 (Direct Cost: ¥2,800,000)
Fiscal Year 2005: ¥2,700,000 (Direct Cost: ¥2,700,000)
Fiscal Year 2004: ¥4,400,000 (Direct Cost: ¥4,400,000)
Fiscal Year 2003: ¥5,300,000 (Direct Cost: ¥5,300,000)
|
|---|
| Keywords | SYSTEM-ON-CHIP / DESIGN FOR TESTABILITY / CONSECUTIVE TESTABILITY / CONSECUTIVE TRANSPARENCY / TEST ARCHITECTURE / TEST ACCESS MECHANISM / CO-OPTIMIZATION / CORE-BAES DESIGN |
|---|
| Research Abstract |
(1) We introduced a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at speed of system clock.
(2) We presented a design-for-testability method that transforms a given SoC into consecutively testable one under power constraint. When a power constraint and a user defined importance ratio between area overhead and test application time are given, the proposed method can create optimal TAM and test schedule for the importance ratio under the power constraint with low computational cost. Experimental results show that the proposed method can achieve area and time co-optimization under power constraint. Moreover, the proposed method can obtain better results for the SoCs without power constraint compared to test bus method and our previous method based on consecutive testability of SoCs.
(3) We proposed a method for power-constrained test scheduling for multi-clock domain SoCs and a method for designing power-aware wrapper for multi-clock domain cores using clock domain partitioning.
(4) We also presented several efficient and effective methods for test generation and design for testability for processor cores, logic cores and memory cores in SoCs.
|
