| Project/Area Number |
15300019
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | KYUSHU UNIVERSITY |
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Principal Investigator |
MATSUNAGA Yusuke Kyushu University, Graduate School of Information Science and Electrical Engineering, Associate Professor, 大学院・システム情報科学研究院, 助教授 (00336059)
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| Co-Investigator(Kenkyū-buntansha) |
YASUURA Hiroto Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (80135540)
MURAKAMI Kzzuaki Kyushu University, Graduate School of Information Science and Electrical Engineering, Professor, 大学院・システム情報科学研究院, 教授 (10200263)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥15,900,000 (Direct Cost: ¥15,900,000)
Fiscal Year 2004: ¥3,200,000 (Direct Cost: ¥3,200,000)
Fiscal Year 2003: ¥12,700,000 (Direct Cost: ¥12,700,000)
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| Keywords | FPGA / technology mapping / logic function manipulation / BDD / DAG-covering / 論理合成 / 関数分解 / 二分決定グラフ / ブーリアン・マッチング |
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| Research Abstract |
Based on a fast algorithm finding disjoint decomposition of a given logic function, we have developed a technology mapping algorithm for FPGA which consists of basic blocks having two 4-LUT s and one 3-LUT. Experimental results show that our algorithm runs 10〜100 times faster than the previous algorithm without using disjoint decomposition algorithm.
We also developed another technology mapping algorithm, which maps a given logic network into a LUT network that has no structural constraints. This algorithm also utilizes a fast disjoint decomposition algorithm, thus it can do logic function manipulation in a reasonable time. From the experiments using benchmark circuits, we found that many functions which have no more than 6 inputs can be implemented with two 4-LUTs. If we do not use logic function manipulation technique, the average number of LUTs required to implement the same functions is 3.5. This shows the effectiveness of our method.
Generally, technology mapping algorithm consists of two components, matching and covering. Matching phase finds matching between subcircuit and LUTs. The above two algorithms enhance this operation. Covering phase finds best (good) combination among matching found in the previous phase. Our last contribution is related to this phase. Theoretically, solving the covering problem exactly is known to be NP-hard, which means that no algorithm exists for solving the problem efficiently. So many technology mapping algorithms use a heuristic that decompose a given circuit into a set of trees, and then try to solve covering problem for each tree. We have developed a new heuristic that does not decompose a circuit, so that it can find better solution than that using tree decomposition. The computational complexity of our algorithm is O(n^2), which is applicable to real industrial circuits.
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