• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques

Research Project

Project/Area Number 15500029
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionTohoku University

Principal Investigator

HANYU Takahiro  Tohoku University, Research Institute of Electrical Communication, Professor, 電気通信研究所, 教授 (40192702)

Co-Investigator(Kenkyū-buntansha) MOCHIZUKI Akira  Tohoku University, Research Institute of Electrical Communication, Research Assistant, 電気通信研究所, 助手 (40359542)
Project Period (FY) 2003 – 2005
Project Status Completed (Fiscal Year 2005)
Budget Amount *help
¥3,800,000 (Direct Cost: ¥3,800,000)
Fiscal Year 2005: ¥300,000 (Direct Cost: ¥300,000)
Fiscal Year 2004: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2003: ¥2,800,000 (Direct Cost: ¥2,800,000)
Keywordsinformation system / information communication engineering / electronic devices / equipments / semiconductor ultra-scaling / system-on-chip / network-on-chip / intra-chip high-speed signaling / multiple-valued encoding / クロック分配 / クロックスキュー / 2線符号化方式 / 非同期通信プロトコル / 双方向同時通信 / チップ内通信 / 2線式 / プロトコル / デュプレックス
Research Abstract

The trend in global interconnection delay such as clock distribution is becoming a significant problem in recent deep submicron VLSI. As CMOS technology scales from one generation to the next, the product of the interconnect resistance and load capacitance is not scaling with technology. One of the possible methods to solve the above interconnection problems is to use asynchronous circuit implementation. Dual-rail encoding is widely used as an encoding style of asynchronous data transfer, where every logical variable is encoded using two wires and timing information is also implicit in the code. Every asynchronous data transfer protocol is based on request-acknowledge handshaking : every transfer features a request action where the initiator starts a transfer, and an acknowledge action allowing the target to respond. In this way, the signals propagate round trip between the transmitter and the receiver, thus the cycle time of data transfer becomes large, which is the problem accompanyi … More ng asynchronous data transfer essentially. If the above procedures are executed simultaneously, the cycle time of the asynchronous data transfer with dual-rail encoding becomes much faster than that of the conventional methods. In this research, a new asynchronous data-transfer protocol, called 2-color "1-pbase" dual-rail encoding, is proposed for high-speed asynchronous data transfer. The 2-color 1-phase encoding has two colors which mean two kinds of data definition "ODD" and "EVEN", and different valid data is detected by transferring codewords which have different color alternately. In this protocol, the receiver as well as the transmitter sends the color information as the request signal, then the data transfer is performed by detecting whether the mutual color information is same or not. Because the both request signals can be sent simultaneously, overlap communication can be done. Since data and color information must be bundled on the same wires in the asynchronous data transfer, it is important to detect valid data from the mixed dual-rail code of data and color information. The use of the proposed encoding makes it easy to merge and detect data and color information by calculating the sum of the codewords. In multiple-valued bidirectional current-mode circuits, since current-mode linear summation can be implemented by wiring without any active devices, the proposed asynchronous circuit becomes simple. Moreover, current signals from both sides can be superposed on the same wires, which is an important characteristic of multiple-valued current-mode logic to realize a control signal multiplexing scheme. The use of comparators with sense amplifier makes it easy to detect the sum of components of the codewords quickly. In fact, it is evaluated in a 0.18um CMOS technology that the data transfer cycle of the proposed asynchronous data-transfer scheme using the multiple-valued current-mode logic circuit is about 1.5-times faster than that of the corresponding binary CMOS implementation under the normalized power dissipation. Less

Report

(4 results)
  • 2005 Annual Research Report   Final Research Report Summary
  • 2004 Annual Research Report
  • 2003 Annual Research Report
  • Research Products

    (73 results)

All 2005 2004 2003 Other

All Journal Article (56 results) Publications (17 results)

  • [Journal Article] Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders2005

    • Author(s)
      N.Onizawa
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 35

      Pages: 138-143

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] O.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits

      Pages: 264-267

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE Journal of Multiple-Valued Logic and Soft Computing 11

      Pages: 481-498

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits2005

    • Author(s)
      T.Takahashi
    • Journal Title

      IEEE Journal of Multiple-Valued Logic and Soft Computing 11

      Pages: 499-518

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders2005

    • Author(s)
      N.Onizawa
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 35

      Pages: 138-143

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] 0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits, Digest of Technical Papers

      Pages: 264-267

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      A.Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11, 5-6

      Pages: 481-498

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits2005

    • Author(s)
      T.Takahashi
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11, 5-6

      Pages: 499-518

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11・5-6

      Pages: 481-498

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Control Signal Multiplexing Based Asychronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits2005

    • Author(s)
      Tomohiro Takahashi
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing 11・5-6

      Pages: 499-518

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 0.2V-Swing Multiple-Valued Differential-Pair Circuit and Its Application to Arithmetic VLSI2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      International Workshop on Post-Binary ULSI Systems 14

      Pages: 35-41

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders2005

    • Author(s)
      Naoya Onizawa
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 35

      Pages: 138-143

    • Related Report
      2005 Annual Research Report
  • [Journal Article] A 1.88ns 54x54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      2005 Symposium on VLSI Circuits, Digest of Technical Papers

      Pages: 264-267

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 多値差動ロジックに基づく高性能4値フリップフロップの構成2005

    • Author(s)
      白濱弘勝
    • Journal Title

      電気関係学会東北支部連合大会講演論文集

      Pages: 319-319

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 電流モード多値回路技術の展望2005

    • Author(s)
      望月 明
    • Journal Title

      多値論理研究ノート 28

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 2線式電流モードNull Convention Logicに基づくDelay-Insensitive非同期VLSIの構成と評価2005

    • Author(s)
      鬼沢直哉
    • Journal Title

      多値論理研究ノート 28

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing (to be published)(印刷中)

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits2005

    • Author(s)
      Tomohiro Takahashi
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing (to be published)(印刷中)

    • Related Report
      2004 Annual Research Report
  • [Journal Article] A 1.88ns 54×54-bit Multiplier in 0.18μm CMOS Based on Multiple-Valued Differential-Pair Circuitry2005

    • Author(s)
      Akira Mochizuki
    • Journal Title

      2005 Sympsium on VLSI Circuits, Digest of Technical Papers (to be published)(印刷中)

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 多値電流モードNull Conventionロジックに基づくコンパクト非同期算術演算回路の構成2005

    • Author(s)
      鬼沢直哉
    • Journal Title

      電子情報通信学会第2種研究会「多値論理とその応用」研究会技術研究報告 MVL-05

      Pages: 61-66

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 多値差動ロジックに基づく高性能部分積生成回路の構成2005

    • Author(s)
      望月明
    • Journal Title

      電子情報通信学会2005年総合大会講演論文集

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans. on Electronics E87-C,4

      Pages: 582-588

    • NAID

      110003214894

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] 双方向同時制御に基づく非同期データ転送方式とそのVLSI実現2004

    • Author(s)
      高橋知宏
    • Journal Title

      電子情報通信学会論文誌C J87-C,5

      Pages: 459-468

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication2004

    • Author(s)
      T.Takahashi
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 20-25

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its application2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      ITC-CSCC 2004

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1876-1883

    • NAID

      110003214804

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1915-1922

    • NAID

      110003214810

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer2004

    • Author(s)
      T.Takahashi
    • Journal Title

      IEICE Trans.on Electronics E87-C,11

      Pages: 1928-1934

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 4

      Pages: 582-588

    • NAID

      110003214894

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Asynchronous Data Transfer Scheme Based on Simultaneous Control in a Bidirectional Way and Its VLSI Design2004

    • Author(s)
      T.Takahashi
    • Journal Title

      IEICE-C (in Japanese) J87-C, 5

      Pages: 459-468

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication2004

    • Author(s)
      T.Takahashi
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 34

      Pages: 20-25

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Infra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its Application2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      ITC-CSCC 2004 6C1L5-1/5-4

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic with Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 11

      Pages: 1876-1883

    • NAID

      110003214804

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Infra-Chip Data Transfer2004

    • Author(s)
      A.Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C, 11

      Pages: 1915-1922

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer2004

    • Author(s)
      T.Takahashi
    • Journal Title

      IEICE Trans.on Electronics E87-C, 11

      Pages: 1928-1934

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C・4

      Pages: 582-588

    • NAID

      110003214894

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 双方向同時制御に基づく非同期データ転送方式とそのVLSI実現2004

    • Author(s)
      高橋知宏
    • Journal Title

      電子情報通信学会論文誌C J87-C・5

      Pages: 459-468

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Low-Power Motion-Vector Detection VLSI Processor Based on Pass-Gate Logic With Dynamic Supply-Voltage/Clock-Frequency Scaling2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics 87-C・11

      Pages: 1876-1883

    • NAID

      110003214804

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Dynamically Function-Programmable Bus Architecture for High-Throughput Intra-Chip Data Transfer2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      IEICE Trans.on Electronics E87-C・11

      Pages: 1915-1922

    • NAID

      110003214810

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Differential Operation Oriented Multiple-Valued Encoding and Circuit Realization for Asynchronous Data Transfer2004

    • Author(s)
      Tomohiro Takahashi
    • Journal Title

      IEICE Trans.on Electronics E87-C・11

      Pages: 1928-1934

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication2004

    • Author(s)
      Tomohiro Takahashi
    • Journal Title

      Proc.34th IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 20-25

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      Proc.34th IEEE International Symposium on Multiple-Valued Logic 34

      Pages: 192-197

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Low-Power Pipelined VLSI System Using a Power-Supply-Controlled CMOS Pass-Gate Network and Its application2004

    • Author(s)
      Akira Mochizuki
    • Journal Title

      ITC-CSCC 2004

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Design of a Multiple-Valued Current-Mode Circuit Based on Signal Multiplexing for Asynchronous Duplex Communication2004

    • Author(s)
      Tomohiro Takahashi
    • Journal Title

      Proc.2nd Student-Organizing International Mini-Conference on Information Electronics System(SOIM-COE04) 2

      Pages: 221-224

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 多値ダイナミック差動論理に基づく高速低電力ALUの構成2004

    • Author(s)
      北村健
    • Journal Title

      平成16年電気関係学会東北支部連合大会講演論文集 2E6

      Pages: 181-181

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 多値非同期データ転送技術に基づくチップ内高速相互結合網の構成2004

    • Author(s)
      鬼沢直哉
    • Journal Title

      平成16年電気関係学会東北支部連合大会講演論文集 2E7

      Pages: 182-182

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 多値2線差動論理に基づく高性能算術演算VLSI2004

    • Author(s)
      望月明
    • Journal Title

      多値論理研究ノート 27

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 電流信号多重化に基づく非同期データ転送LSIの実現2004

    • Author(s)
      高橋知宏
    • Journal Title

      多値論理研究ノート 27

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 33

      Pages: 99-104

    • NAID

      120001182150

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE International Symposium on Multiple-Valued Logic 33

      Pages: 207-212

    • NAID

      120001182151

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 33

      Pages: 99-104

    • NAID

      120001182150

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Journal Article] Multiple-Valued Dynamic Source-Coupled Logic2003

    • Author(s)
      T.Hanyu
    • Journal Title

      IEEE Int.Symposium on Multiple-Valued Logic 33

      Pages: 207-212

    • NAID

      120001182151

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2005 Final Research Report Summary
  • [Publications] Tsukasa Ike: "Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization"Journal of Multiple-Valued Logic & Soft Computing. 9・1. 5-21 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Hiromitsu Kimura: "Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and Its Applications"Journal of Multiple-Valued Logic & Soft Computing. 9・1. 23-42 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Takahiro Hanyu: "Multiple-Valued Dynamic Source-Coupled Logic"Proc.IEEE International Symposium on Multiple-Valued Logic. 33. 207-212 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Takahiro Hanyu: "Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current-Mode Logic"Proc.IEEE International Symposium on Multiple-Valued Logic. 33. 99-104 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Tomohiro Takahashi: "High-Speed Asynchronous Data Transfer Scheme Based on 2-Color 1-Phase Dual-Rail Coding and Its VLSI Design"Proc.1st Student-Organizing International Mini-Conference on Information Electronics System. 298-302 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 西ノ原大介: "相補形パスゲートロジックに基づく低消費電力VLSIシステムの構成"平成15年度電気関係学会東北支部連合大会講演論文集. 2G1. 243 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 佐藤宏則: "ソースカップルドロジックに基づく高性能多値集積回路の構成"平成15年度電気関係学会東北支部連合大会講演論文集. 2G3. 245 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 竹内祟: "パケット形式に基づくチップ内データ転送"平成15年度電気関係学会東北支部連合大会講演論文集. 2G5. 247 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 望月明: "信号・しきい値多重化に基づく高性能電流モード多値回路の構成"多値論理とその応用研究会技術研究報告. MVL-04・1. 99-105 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 望月明: "差動対ツリー構造に基づく多値論理回路網の系統的設計"多値論理フォーラム、多値論理研究ノート. 26. 6-1-6-6 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 望月明: "高速低電力多値電流モード回路の展望"第2回次世代VLSIコンピューティングとシステムインテグレーション(NGC)研究会. 講演番号4. (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Akira Mochizuki: "Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control"IEICE Trans.on Electronics. E87-C・4(to be published). (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 高橋知宏: "双方同時制御に基づく非同期データ転送方式とそのVLSI実現"電子情報通信学会論文誌C(採録決定、2004年5月掲載予定). J87-C・5. (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] Tomohiro Takahashi: "Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication"Proc.IEEE International Symposium on Multiple-Valued Logic. 34(to be published). (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 竹内祟: "自律分散制御に基づくチップ内高速データ転送方式"電子情報通信学会技術報告. ICD2003-221. 33-37 (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 望月明: "基盤バイアス制御に基づく低電力多値集積回路の構成"電子情報通信学会2004年総合大会講演論文集. SC-11-11. S-7-S-8 (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 高橋知宏: "電流モード制御信号多重化に基づく高速非同期データ転送LSIの試作"電子情報通信学会2004年総合大会講演論文集. SC-11-12. S-9-S-10 (2004)

    • Related Report
      2003 Annual Research Report

URL: 

Published: 2003-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi