A Study on Efficient Problem Solving for Combinatorial Problems Using Programmable Logic Devices
| Project/Area Number |
15500040
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
WAKABAYASHI Shinichi Hiroshima City University, Faculty of Information Sciences, Professor, 情報科学部, 教授 (50210860)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2004: ¥2,200,000 (Direct Cost: ¥2,200,000)
Fiscal Year 2003: ¥1,500,000 (Direct Cost: ¥1,500,000)
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| Keywords | FPGA / combinatorial problem / NP-hard / branch and bound / instance-specific / hardware solver / プログラム可能論理デバイス / 論理合成 / 最大クリーク |
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| Research Abstract |
Reconfigurable computing with Field Programmable Gate Arrays (FPGAs) has become popular as a new approach to combinatorial problems. In particular, problem solving by instance-specific accelerators has been widely noticed such as the Boolean satisfiability problem, the minimum cover problem, etc. In this study, we present a novel approach to solving several NP-hard problems on graphs such as the maximum clique problem, the minimum vertex cover problem, and the minimum dominating set problem, based on reconfigurable computing. In the proposed approach, for a given instance of each problem, an HDL description of an instance-specific accelerator is generated to produce an optimum solution of the problem. The generated instance-specific accelerator is based on branch & bound search with various pruning techniques. Furthermore, pipeline and parallel processing are introduced to speed up the computation time. We also developed a system, which generates the Verilog HDL description of the accelerator automatically for a given problem instance. The generated Verilog description is compiled and downloaded to an FPGA as configuration data to solve the problem by hardware. Experimental results showed that, compared with the software solver, the proposed algorithm produced an optimum solution of the problem in a 'very shorter running time even if the time for circuit synthesis and configuration of FPGA was taken into account.
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Report
(3 results)
Research Products
(17 results)
