Study on Built-in Self Test and Fault Diagnosis for Very High Speed and Deep Sub-micron VLSIs
| Project/Area Number |
15500043
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Ehime University |
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Principal Investigator |
TAKAMATSU Yuzo Ehime University, Faculty of Engineering, Professor, 工学部, 教授 (80039255)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI Hiroshi Ehime University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (80226878)
HIGAMI Yoshinobu Ehime University, Faculty of Engineering, Associate Professor, 工学部, 助教授 (40304654)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥3,700,000 (Direct Cost: ¥3,700,000)
Fiscal Year 2005: ¥700,000 (Direct Cost: ¥700,000)
Fiscal Year 2004: ¥1,200,000 (Direct Cost: ¥1,200,000)
Fiscal Year 2003: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Keywords | Testing of LSIs / Fault diagnosis / Built-in self test / Test compaction / Stuck-at fault / Internal bridging fault / Open fault / 論理回路のテスト / 故障検査 / ブリッジ故障 / クロストーク故障 / ドントケア値 / VLSIの故障検査 / VLSIの故障診断 / 遅延故障 / テスト系列圧縮 / 消費電力削減 |
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| Research Abstract |
We have developed a diagnostic test compaction method, a fault diagnostic method for open faults and a fault diagnostic method for internal bridging faults.
(1)Diagnostic test compaction method
In built-in self test of LSIs, a large number of test vectors must be applied. We have developed a method for selecting a small number of test vectors used for diagnosis of faulty LSIs. This method can reduce the execution time for fault diagnosis as well as memory space to store test data and output responses. The developed method selects a small number of test vectors among a given test set so that the number of fault pairs distinguished by the given test set is preserved. First, it extracts faults that are detected by only one test vector, and collect the test vectors that detect such faults. After that, a subset of fault pairs are selected and a small number of test vectors are selected so that the selected fault pairs are distinguished by the test vectors. The process of selection of fault pairs and test vectors is repeated until all the fault pairs are distinguished.
(2)Fault diagnostic method for open faults
We have developed a diagnostic method for open faults. In this research, we assumed that the value at a signal line with open fault is determined by adjacent signal lines. The developed method perform fault simulation using passing tests and failing tests, and deduces a small number of candidate faulty sites.
(3)Fault diagnostic method for internal bridging faults
We have developed a diagnostic method for internal bridging faults, which are caused by short between two transistor nodes. The developed method first performs logic simulation using passing tests in order to extract suspected faulty gates. Next, it deduces suspected internal bridging faults existing in the suspected faulty gates. Moreover, it reduces the suspected internal bridging faults by performing logic simulation using passing tests.
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Report
(4 results)
Research Products
(16 results)
