| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2005: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2004: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 2003: ¥1,000,000 (Direct Cost: ¥1,000,000)
|
|---|
| Research Abstract |
The aim of this research is to develop a reconfigurable LSI system and LSI CAD (Computer-Aided Design) tools for statistical genetic algorithms. We have proposed a thread partitioning algorithm in low power high-level synthesis, a cosynthesis algorithm for applicaton specific processors with heterogeneous datapaths, instruction set and functional unit synthesis for SIMD processor cores, FPGA-based reconfigurable adaptive FEC, high-level power optimization based on thread partitioning, a hybrid dictionary test data compression for multiscan-based designs, a selective scan chain reconfiguration through run-length coding for test data compression and scan power reduction, a reconfigurable adaptive FEC system for reliable wireless communications, experimental evaluation of high-level energy optimization based on thread partitioning, a new correction for multiple comparisons in genome-wide case-control association studies based on haplotypes and diplotype configurations, a processor core synthesis system in IP-based SoC design, sub-operation parallelism optimization in SIMD processor synthesis and its experimental evaluations, A SIMD instruction set and functional unit synthesis algorithm with SIMD operation decomposition, an interface-circuit synthesis method with configurable processor core in IP-based SoC designs, FCSCAN : an efficient multiscan-based test compression technique for test cost reduction, a fast elliptic curve cryptosystem LSI embedding word-based Montgomery multiplier, etc.Reconfigurable LSI systems for statistical genetic algorithms have not been developed yet, but enough technics to develop them areobtained in this research.
|
