• Search Research Projects
  • Search Researchers
  • How to Use
  1. Back to previous page

Highly Parallel Network Processor Based on Self Timed Pipeline Circuit

Research Project

Project/Area Number 15500056
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionKochi University of Technology

Principal Investigator

IWATA Makoto  Kochi University of Technology, Dept.of Information Systems Engineering, Professor, 工学部, 教授 (60232683)

Project Period (FY) 2003 – 2004
Project Status Completed (Fiscal Year 2004)
Budget Amount *help
¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 2004: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 2003: ¥2,000,000 (Direct Cost: ¥2,000,000)
KeywordsSelf-timed circuit / Data-driven architecture / Network processor / Class based QoS control / Packet classification / Signature matching / Macroflow model / セルフタイム型回路 / ファイアウォール / IDS / IPパケット分類 / パイプライン / 優先キューイング / Diffserv
Research Abstract

The objectives of this research project is to establish a flexible architecture of highly integrated network processor drip by exhaustively utilizing the self-timed pipeline as one of low-power, easily designed and high performance circuits. A part of the project has been conducted through developing and evaluating a newly designed LSI. The following basic research results have been obtained in this Project by applying the proposed architecture to the class based QoS control function like Diffserv and the high-level packet filtering such as that of firewall and intruder detection systam (IOS).
1 Self-Timed priocity queueing mechanism
We proposed a self-timed priority queueing mechanism in which every pair of stage of a folded pipeline has a bypass stage to minimize queueing delay time. We observed that the test chip fabricated by 0.18 um CMOS process could achieve around 100 M IP packets/s with 8 different classes.
2 Data-driven implementation of high-speed packet filtering
We proposed two data-driven implementations one is a static filtering of layer 4 packet header and the other one is a signature matching for payload inspection. Our evaluation results showed that 4 M packets/s for the static filtering and 0.1 M packets/s for the signature matching could be achieved on only one date-driven processor. Additional circuit cost of some dedicated instructions for the static filtering was evaluated by implementing a self-timed data-driven processor on FPGA. The result indicated that only 6 % increase of gates was enough to realize the proposed architecture.
3 Performance estimation model of the self-timed pipelined systems
We formulated a macro flow model by which the behavior of ever packet flowing in a self-timed pipeline can be modeled simply. Using this model, we can reduce simulation time of the self-timed pipelined systems in half with reasonable accuracy in comparison to the existing naive model.

Report

(3 results)
  • 2004 Annual Research Report   Final Research Report Summary
  • 2003 Annual Research Report
  • Research Products

    (23 results)

All 2004 2003 Other

All Journal Article (17 results) Publications (6 results)

  • [Journal Article] 100MPackets/s Fully Self-Timed Priority Queue : FQ2004

    • Author(s)
      Makoto IWATA
    • Journal Title

      Proc.of International Solid-State Circuits Conference 8.1

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] 自己タイミング型パイプラインによる優先キューイング制御方式2004

    • Author(s)
      林 秀樹
    • Journal Title

      電子情報通信学会論文誌B J87-B・6

      Pages: 1063-1075

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] 異種混合ネットワークにおける自律型フロー分散制御方式2004

    • Author(s)
      林 秀樹
    • Journal Title

      情報処理学会論文誌 45・2

      Pages: 426-437

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Super-Pipelined Implementation of IP Packet Classification2004

    • Author(s)
      Daichi MORIKAWA
    • Journal Title

      Journal of Intelligent Automation and Soft Computing 10・2

      Pages: 175-184

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Design Concept of An Embedded Data-Driven Firewall Processor2004

    • Author(s)
      Makoto IWATA
    • Journal Title

      Proc.of International Conference on next Era Information Networking

      Pages: 80-87

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] A Priority Queueing Scheme Based on Self-Timed Pipeline (in Japanese)2004

    • Author(s)
      Hideki HAYASHI
    • Journal Title

      Transaction on Communication, IEICE vol.J87-B, no.6

      Pages: 1063-1075

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Autonomous Flow Distribution Control in Homogeneous Network (in Japanese)2004

    • Author(s)
      Hideki HAYASHI
    • Journal Title

      Transaction on Information Processing Society vol.45, no.2

      Pages: 426-437

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Super-Pipelined Implementation of IP Packet Classification2004

    • Author(s)
      Daichi MORIKAWA
    • Journal Title

      Journal of Intelligent Automation and Soft Computing vol.10, no.2

      Pages: 175-184

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] Design Concept of An Embedded Data-Driven Firewall Processor2004

    • Author(s)
      Makoto IWATA
    • Journal Title

      Proc.of International Conference on Next Era Information Networking

      Pages: 80-87

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] 自己タイミング型パイプラインによる優先キューイング方式2004

    • Author(s)
      林 秀樹
    • Journal Title

      電子情報通信学会論文誌B-I J87-B・8

      Pages: 1063-1075

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Super-Pipelined Implementation of IP Packet Classification2004

    • Author(s)
      Daichi Morikawa
    • Journal Title

      Journal of Intelligent Automation and Soft Computing 10・2

      Pages: 175-184

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Design Concept of An Embedded Data-Driven Firewall Processor2004

    • Author(s)
      Makoto Iwata
    • Journal Title

      International Conference on Next Era Information Networking NEINE' 04

      Pages: 80-87

    • Related Report
      2004 Annual Research Report
  • [Journal Article] A Fast Simulation Scheme for Self-Timed Super-Pipelined Systems2004

    • Author(s)
      Shuji Sannomiya
    • Journal Title

      International Conference on Next Era Information Networking NEINE' 04

      Pages: 127-138

    • Related Report
      2004 Annual Research Report
  • [Journal Article] 100M packets/sec自己タイミング型優先キュー:FQ2004

    • Author(s)
      岩田 誠
    • Journal Title

      電子情報通信学会集積回路研究会 ICD2004-32

      Pages: 53-58

    • NAID

      110003316509

    • Related Report
      2004 Annual Research Report
  • [Journal Article] セルフタイム回路によるデータ駆動型プロセッサとその応用2004

    • Author(s)
      岩田 誠
    • Journal Title

      電子情報通信学会集積回路研究会 ICD2004-197

      Pages: 25-30

    • NAID

      110003318226

    • Related Report
      2004 Annual Research Report
  • [Journal Article] A Macroscopic Behavior Model for Self-Timed Pipeline Systems2003

    • Author(s)
      Shuji SANNOMIYA
    • Journal Title

      Proc.of the Seventeenth Workshop on Parallel and Distributed Simulation

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Journal Article] 100 M Packets/s Fully Self-Timed Priority Queue : FQ

    • Author(s)
      Makoto IWATA
    • Journal Title

      Proc.of International Solid-State Circuits Conference, 8.1, 2004

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2004 Final Research Report Summary
  • [Publications] Sannomiya, Shuji: "A Macroscopic Behavior Model for Self-Timed Pipeline Systems"Proc. of the Seventeenth Workshop on Parallel and Distributed Simulation. 133-140 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 林 秀樹: "クラス別QoS制御向き自己同期型優先キューの性能評価"情報技術レターズ. 313-312 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] 林 秀樹: "異種混合ネットワークにおける自律型フロー分散制御方式"情報処理学会論文誌. 45・2. 426-437 (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] Ruck Thawonmas: "A Novel Parallel Model for Self-Organizing Maps and Its Efficient Implementation on a Data-Driven Multiprocessor"Journal of Advanced Computational Intelligence. 7・3. 355-361 (2003)

    • Related Report
      2003 Annual Research Report
  • [Publications] Makoto Iwata: "100MPackets/s Fully Self-Timed Priority Queue : FQ"Proc. of International Solid-State Circuits Conference. 8.1. (2004)

    • Related Report
      2003 Annual Research Report
  • [Publications] 林 秀樹: "自己タイミング型パイプラインによる優先キューイング制御方式"電子情報通信学会論文誌B. J87-B・6. (2004)

    • Related Report
      2003 Annual Research Report

URL: 

Published: 2003-04-01   Modified: 2016-04-21  

Information User Guide FAQ News Terms of Use Attribution of KAKENHI

Powered by NII kakenhi