| Project/Area Number |
15500149
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Sensitivity informatics/Soft computing
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| Research Institution | Tsukuba University of Technology (2005)
Tsukuba College of Technology (2003-2004) |
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Principal Investigator |
TATSUMI Hisayuki Tsukuba University of Technology, Faculty of Health Science, Associate Professor, 保健科学部, 助教授 (30188271)
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| Co-Investigator(Kenkyū-buntansha) |
TOKUMASU Shinji Kanagawa Institute of Technology, Professor, 情報学部, 教授 (00278029)
MIYAKAWA Masahiro Tsukuba University of Technology, Faculty of Health Science, Professor, 保健科学部, 教授 (70248748)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥3,000,000 (Direct Cost: ¥3,000,000)
Fiscal Year 2005: ¥500,000 (Direct Cost: ¥500,000)
Fiscal Year 2004: ¥1,400,000 (Direct Cost: ¥1,400,000)
Fiscal Year 2003: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Keywords | Neural network / Fault diagnosis / Logical circuit / Error back propagation / Gate fault / Learning / プランニング / 誤差逆伝搬法 |
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| Research Abstract |
The purpose of this research is to develop and apply a new fault diagnosis method of electronic logical circuits. Neural net not only can detect faults of circuits but also it is fault-resistive. We have applied this property to fault diagnosis. The method is simple and found universally applicable to most types of faults. Our method is unique in that it requires neither a specially prepared test data set nor any fault diagnosis dictionary, of which property used to be observed commonly in other fault diagnosis method.
Previous approach of fault diagnosis adheres to completeness of the diagnosibility, i.e., it requires either to generate a test pattern that can detect existence of a single fault or to prove that it is not possible to diagnose a fault. On the other hand, our method enumerates candidates of fault corrections one by one, though the diagnosis may be erroneous. Though no complete diagnosibility is guaranteed, our method allows a simple detection and diagnosis of fault simultaneously.
Previously we had designed a fault diagnosis algorithm and had obtained an excellent simulation result on small sized circuits. So we have examined what kind of fault model our method can capture. As a result we have observed by experiment that a single static fault (including 0/1 degenerate fault and delay fault) can be detected/diagnosed successfully. We are encouraged by this result and we are currently investigating its reason. As a natural consequence, to exploit the diagnosibility ability in our neural net approach, we want to develop an algorithm to diagnose dynamic fault. We also want to extend target fault models of our method somehow by employing multiple-valued logic, which possesses much versatile expressibility compared to the binary case.
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