| Project/Area Number |
15560281
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Hosei University |
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Principal Investigator |
HARA Tohru Hosei University, Engineering, Professor, 工学部, 教授 (00147886)
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| Co-Investigator(Kenkyū-buntansha) |
YAMAMOTO Yasuhiro Hosei University, Engineering Department, Professor, 工学部, 教授 (50139383)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥3,500,000 (Direct Cost: ¥3,500,000)
Fiscal Year 2004: ¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2003: ¥1,800,000 (Direct Cost: ¥1,800,000)
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| Keywords | LSI's / Cu interconnection layer / High speed logic LSI / Electroplating / Low resistivity Cu layer / Copper-hexafluoro-silicate electrolytic solution / 銅配線 / メッキ膜 / 比抵抗低減 / 薄膜 / 核生成制御 / 超LSI / 配線層 / 銅メッキ / 比抵抗 |
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| Research Abstract |
Propagation delay time in advanced logic LSI's is determined mainly by the CR time constant in the multi-level interconnection. Therefore, reduction of interconnection resistance with employing Cu layer is the most important factor to manufacture high speed LSI's. Although resistivity increases markedly with decreasing line width in the Cu interconnection layers, specifically at widths below 100 nm, little works have been done for the reduction of resistivity. Quantitative measurement of resistivity is also difficult in this interconnection layer. This work indicates clearly that resistance of 60 nm wide Cu Damascene line is determined by that of 16 nm thick nucleated Cu layer.
Resistivity is 3 μΩ-cm in 300 nm thick Cu layers. It increases rapidly with decreasing thickness and reaches 12 μΩ-cm at thickness of 50 nm. This increase is due to the reduction of grain size and (200) orientation, increasing of stress and also to the inhomogeneous nucleation. It has been found that resistivity
… More
of 16 nm thick nucleated layer is important in the manufacturing of 60 nm wide Cu Damascene interconnection lines. Low resistivity 16 nm thick Cu interconnection layer can be electroplated when the nucleation on the seed layer can be achieved uniformly. Uniform nucleation has practically been studied with employing newly developed electrolytic solution of copper-hexafluoro-silicate. This improvement can also be attained by the surface cleaning of Cu seed layer, optimization of additive contamination, deposition and formation of low stress seed layer and also by the deposition of low stress barrier layer instead of conventional barrier layer of TaN. Relation of these process parameters with the resistivity of thin Cu layer has been studied quantitatively in this work.
As a result of these fundamental research works, resistivity of 50 nm thick Cu layer decreases from 12 μΩ-cm in conventional layer to 3 μΩ-cm in this layer developed by us. These processes are very useful for the electroplating of low resistivity 16 nm thick Cu layers. Three time higher speeds can be attained when this Cu Damascene interconnection line is used. Less
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