Asynchronous Pulse-type Chaotic Neural Networks with Hardware Models
| Project/Area Number |
15560308
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Nihon University |
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Principal Investigator |
SAEKI Katsutoshi Nihon University, College of Science and Technology, Assistant Professor, 理工学部, 講師 (60256807)
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| Co-Investigator(Kenkyū-buntansha) |
SEKINE Yoshifumi Nihon University, College of Science and Technology, Professor, 理工学部, 教授 (90059965)
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| Project Period (FY) |
2003 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2005: ¥1,500,000 (Direct Cost: ¥1,500,000)
Fiscal Year 2004: ¥1,100,000 (Direct Cost: ¥1,100,000)
Fiscal Year 2003: ¥1,000,000 (Direct Cost: ¥1,000,000)
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| Keywords | Pulse-type / Neuron model / Negative resistance / Multiple valued memory cell / Hardware active dendrite model / CPG model / STDP / Ring neural network / 可塑性 / ニューラルネットワーク / 環状 / アナログ / ハードウェア / カオス / FPGA / DSP |
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| Research Abstract |
Brain subsystems have a high degree of information processing ability, namely recognition and learning. However, the information processing functions have not been clarified as yet. As a result, various neuron models and artificial neural networks have been studied in order to clarify the information processing functions of biological neural networks, and apply them to engineering problems. Artificial neural networks performing similarly to the human brain are required for constructing an information processing system of brain-type using the VLSI technology.
In this study, we discuss asynchronous pulse-type chaotic neural networks with hardware models.
Results,
(1)In our proposed hardware active dendrite model, it is shown clearly that the active dendrite model has similar biological backpropagation characteristics (References No.1).
(2)We propose the CMOS implementation of a multiple valued memory cell using A-shaped negative resistance devices for plastic synapses (References No.2).
(3)We construct a short-term memory circuit, and we verify the memory patterns of the temporal pattern recognition circuit using hardware ring neural networks (References No.3).
(4)We investigate the effect of STDP on the ability to extract phase information buried in fluctuation. We focus on spike timing dependent synaptic plasticity (STDP), and we construct neural networks from a pulse-type hardware neuron model using STDP. We show that phase information buried in fluctuation is revealed by the effect of STDP, making it possible to decode the synaptic weight. Moreover, we show that it is possible to extract the phase difference buried in fluctuation representing the reinforcement part of the synaptic weight, using neural networks with STDP.
(5)It is shown that generation and transition of oscillation patterns are possible by giving external inputs of one pulse to the CPG (Central Pattern Generator) model (References No.4).
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Report
(4 results)
Research Products
(13 results)
