A study of a method to improve the productivity of mixed semiconductor manufacturing
| Project/Area Number |
15560350
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
System engineering
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| Research Institution | University of Aizu |
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Principal Investigator |
SAITO Kazuyuki University of Aizu, School of Computer Science and Technology, Professor, コンピュータ理工学部, 教授 (60254083)
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| Project Period (FY) |
2003 – 2004
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| Project Status |
Completed (Fiscal Year 2004)
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| Budget Amount *help |
¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2004: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2003: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | Semiconductor Manufacturing / Resource Planning / Dispatch / Simulation / Petri Net / Response Time / Adjustment / 半導体製造技術 / 多品種生産 / 優先度割付け法 / スループット |
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| Research Abstract |
I performed this project from fo11owing two view points; a research on a dispatching algorithm, and a research on a development of a manufacturing simulator.
A new dispatching algorithm for dynamic allocation of Work-In-Process (WIP) named Pseudo Periodical Priority Dispatching (P3D) is proposed. Performance parameters, adjustment rate, throughput, response time and tardiness, when applying P3D are studied and compared with the results of FCFS and SPT by simulations assuming a Poisson arrival. The adjustment rate is the minimum is P3D. P3D is effective both in the bottleneck modeled processing step and in the non-bottleneck modeled processing step. Especially in the bottleneck modeled processing step, although the average response time of SPT is minimum, that for P3D is about 65% of that for FCFS and the tardiness for P3D is about 28% of that for SPT. Then P3D is confirmed that the fair dispatching is achieved. Finally the author concluded that P3D is an effective dispatching algorithm in the case of the broad product-mix.
The manufacturing simulator is developed based on a color Petri Net theory. The semiconductor manufacturing system can be described by a loop-type net, although the system has more than 300 processing steps. However, new mechanisms are required for describing the semiconductor manufacturing system. A new attributes shall be defined for the tokens corresponding to the processing step, and attribute for the transition shall be defined by referring the sequence table for the LSI fabrication. Also I have proposed some new component for the Petri Net to describe the system easily.
The evaluation in the actual semiconductor facilities will be the future subject of this research.
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Report
(3 results)
Research Products
(14 results)
