| Budget Amount *help |
¥45,110,000 (Direct Cost: ¥34,700,000、Indirect Cost: ¥10,410,000)
Fiscal Year 2017: ¥9,100,000 (Direct Cost: ¥7,000,000、Indirect Cost: ¥2,100,000)
Fiscal Year 2016: ¥8,840,000 (Direct Cost: ¥6,800,000、Indirect Cost: ¥2,040,000)
Fiscal Year 2015: ¥27,170,000 (Direct Cost: ¥20,900,000、Indirect Cost: ¥6,270,000)
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| Outline of Final Research Achievements |
Performance of LSI devices has been continuously improved by shrinking device components. Recent devices encounter a problem of forming very narrow multilayer interconnections. In this project, we found the conditions to form 15 nm wide interconnections (M2 lines and vias) by a dynamic nano-reflow method of depositing Cu alloy at elevated temperatures. With this method, an alloying element was segregated at Cu/insulator interface and enhanced the wettability of the deposited metals. We also found that controlling parameters are surface curvature gradient in the initial deposition stage and thermal stress gradient during heating and cooling. The effects of each driving force are nearly the same magnitude. Based on the obtained results, we could simulate reflow behavior.
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