Reconfigurable Architectures for Accelerating Data Mining

• Project/Area Number: 15H02673
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system
• Research Institution: Hokkaido University
• Principal Investigator: Motomura Masato 北海道大学, 情報科学研究科, 教授 (90574286)
• Co-Investigator(Kenkyū-buntansha): 有村 博紀 北海道大学, 情報科学研究科, 教授 (20222763)
• Project Period (FY): 2015-04-01 – 2019-03-31
• Project Status: Discontinued (Fiscal Year 2018)
• Budget Amount: ¥17,940,000 (Direct Cost: ¥13,800,000、Indirect Cost: ¥4,140,000); Fiscal Year 2018: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000); Fiscal Year 2017: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2016: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2015: ¥5,070,000 (Direct Cost: ¥3,900,000、Indirect Cost: ¥1,170,000)
• Keywords: ビッグデータ / データマイニング / イジングモデル / 組合せ最適化問題 / リコンフィギュラブルシステム / グラフ処理 / リコンフィギュラブル / ストリーム処理

Outline of Final Research Achievements

We have conducted researches of architectures for combinatory optimization problems. Conventional idea has been to conduct minor-embedding or a target graph onto hardware graph that is more sparse than the former. Our new architectural proposal is to time-multiplexing a hardware structure for expanding hardware graph, that is powerful enough to sustain the original denser target graph. This idea has been verified to achieve higher accuracy for large graphs in our simulation.

Academic Significance and Societal Importance of the Research Achievements

IoT 社会の到来により、データマイニングに代表されるビッグデータ処理が計算処理の中心的課題となりつつある。本研究は、(1)データマイニング処理に適したリコンフィギュラブルアーキテクチャと、(2)HW アーキテクチャを考慮したデータマイニングアルゴリズムの二つの課題に統括的に取り組むことで、超高速・低電力なデータマイニング処理基盤の確立を目指すものである。

Research Products

• [Journal Article] Mainly static/partially dynamic reconfigurable array accelerator towards energy-efficient embedded microprocessor (2017)
  • Author(s): Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., and Asai T.
  • Journal Title: Circuits and Systems Volume: Vol.8
  • Peer Reviewed / Open Access
• [Journal Article] FPGA-based stream processing for frequent itemset mining with incremental multiple hashes (2016)
  • Author(s): Yamamoto K., Ikebe M., Asai T., and Motomura M.,
  • Journal Title: Circuits and Systems Volume: V0l. 7 Issue: 10 Pages: 3299-3309
  • DOI: 10.4236/cs.2016.710281
  • Peer Reviewed / Open Access / Acknowledgement Compliant
• [Presentation] A Time-Division Multiplexing Ising Machine on FPGAs (2017)
  • Author(s): amamoto K., Huang W., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M.
  • Organizer: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017)
  • Place of Presentation: Ruhr University, Bochum, Germany
  • Year and Date: 2017-06-07
  • Int'l Joint Research
• [Presentation] 時分割多重機構を用いた高密度FPGAイジングマシン (2017)
  • Author(s): 山本 佳生, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人
  • Organizer: 電子情報通信学会コンピュータシステム研究会 (CPSY)
  • Place of Presentation: 登別温泉第一滝本館
  • Year and Date: 2017-05-23
• [Presentation] メモリアクセスパターンを考慮した遅延評価によるZDD構築の高速化 (2017)
  • Author(s): 熊澤 輝顕, 高前田 伸也, 池辺 将之, 浅井 哲也, 本村 真人
  • Organizer: 第30回 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場, (北九州)
  • Year and Date: 2017-05-11
• [Presentation] A scalable ising model implementation on an FPGA (2017)
  • Author(s): Yamamoto K., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M.
  • Organizer: COOL Chips 20
  • Place of Presentation: Yokohama Media & Communications Center, Yokohama
  • Year and Date: 2017-04-19
  • Int'l Joint Research
• [Presentation] Time-Division Multiplexing (2017)
  • Author(s): Yamamoto K., Ikebe M., Asai T., Motomura M., and Takamaeda-Yamazaki S.,
  • Organizer: GI-CoRE GSQ, GSB, & IGM Joint Symposium -Quantum, Informatics, Biology, & Medicine
  • Int'l Joint Research
• [Presentation] A Time-Division Multiplexing Ising Machine on FPGAs (2017)
  • Author(s): Yamamoto K., Huang W., Takamaeda-Yamazaki S., Ikebe M., Asai T., and Motomura M.
  • Organizer: nternational Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2017)
  • Int'l Joint Research
• [Presentation] 高次数イジングネットワークの時分割処理方式の検討 (2017)
  • Author(s): 山本 佳生, 熊澤 輝顕, 池辺 将之, 浅井 哲也, 本村 真人, 高前田 伸也
  • Organizer: 電子情報通信学会コンピュータシステム研究会 (CPSY)
• [Presentation] 時分割多重機構を用いた高密度FPGAイジングマシン (2017)
  • Author(s): 山本 佳生, 池辺 将之, 浅井 哲也, 本村 真人, 高前田 伸也
  • Organizer: 電子情報通信学会コンピュータシステム研究会 (CPSY)
• [Presentation] AI応用がもたらすプロセッサLSIのゲームチェンジ (2017)
  • Author(s): 本村 真人
  • Organizer: CRDSシンポジウム IoT/AI時代にむけたテクノロジー革新
  • Place of Presentation: Marunouchi Hall & Conference, Tokyo, Japan
  • Invited
• [Presentation] Rise of deep neural network accelerators (2017)
  • Author(s): Motomura M
  • Organizer: Workshop on Brain-inspired Hardware
  • Place of Presentation: AIST Tokyo waterfront Annex building, Tokyo, Japan
  • Int'l Joint Research / Invited
• [Presentation] Hardware architecture for online frequent items mining with memory-efficient data structure, (2016)
  • Author(s): Yamamoto K., Asai T., and Motomura M
  • Organizer: COOL Chips XIX
  • Place of Presentation: Yokohama Media & Communications Center, Yokohama, Japan
  • Year and Date: 2016-04-20
  • Int'l Joint Research
• [Presentation] 知的情報処理を加速するハードウェア技術 (2015)
  • Author(s): 本村真人
  • Organizer: STARCフォーラム2015
  • Place of Presentation: Shin Yokohama Hokusai Hotel, Yokohama, Japan
  • Year and Date: 2015-11-27
  • Invited
• [Presentation] An accelerator for frequent Itemset mining from data stream with parallel item tree (2015)
  • Author(s): Yamamoto K., Fukuda E.S., Asai T., and Motomura M
  • Organizer: The 19th Workshop on Synthesis And System Integration of Mixed Information Technologies
  • Place of Presentation: Evergreen Resort Hotel, Yilan, Taiwan
  • Year and Date: 2015-05-16
  • Int'l Joint Research