| Budget Amount *help |
¥13,520,000 (Direct Cost: ¥10,400,000、Indirect Cost: ¥3,120,000)
Fiscal Year 2017: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2016: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2015: ¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
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| Outline of Final Research Achievements |
There is growing demand for ultra-high-speed serial electric interconnects for data centers and throughout the IT infrastructure. However, in such high-speed serial links, channel distortion which arises from the limited channel bandwidth, and noise significantly restricts the total VLSI system performance.
This research proposes network-centric VLSI system design based on sophisticated coding and signal processing techniques to overcome the problems. In particular, we consider the high-speed data transmission techniques based on PAM-4 signaling that is adopted in the next-generation high-speed signal transmission standard. The main research results are (1) consideration and demonstration of waveform equalization algorithm for PAM-4 data transmission and (2) evaluation of signal integrity by statistical eye pattern measurement of PAM-4 signaling.
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