Hardware Synthesis from OpenCL Programs

• Project/Area Number: 15H02680
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system
• Research Institution: Ritsumeikan University
• Principal Investigator: Tomiyama Hiroyuki 立命館大学, 理工学部, 教授 (80362292)
• Co-Investigator(Kenkyū-buntansha): 谷口 一徹 大阪大学, 情報科学研究科, 准教授 (40551453)
• Research Collaborator: Dutt Nikil
• Project Period (FY): 2015-04-01 – 2019-03-31
• Project Status: Completed (Fiscal Year 2018)
• Budget Amount: ¥15,990,000 (Direct Cost: ¥12,300,000、Indirect Cost: ¥3,690,000); Fiscal Year 2018: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000); Fiscal Year 2017: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000); Fiscal Year 2016: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000); Fiscal Year 2015: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
• Keywords: LSI設計技術 / 並列処理 / 設計自動化

Outline of Final Research Achievements

We have developed multi/manycore architectures which efficiently execute parallel applications written in OpenCL. The developed architectures are customizable for the given applications. We have implemented the architectures on FPGA boards and evaluated their performance by actually executing a set of applications on the FPGA boards. We have also developed techniques for mapping and scheduling parallel tasks on multi/manycore architectures.

Academic Significance and Societal Importance of the Research Achievements

近年、CPUコア単体の性能は頭打ちになっており、汎用計算機だけでなく組込みシステムにおいても、複数または多数のCPUコアを搭載したマルチコア／メニーコア・アーキテクチャが普及している。本研究の社会的な意義は、高性能で安価なマルチコア／メニーコア組込みシステムを短期間で設計することを可能とすることである。一方、学術的には、可変な並列度を持つタスクのスケジューリングに関して、理論的な基礎を確立した。

Research Products

• [Int'l Joint Research] The University of New South Wales(オーストラリア)
• [Int'l Joint Research] University of California, Irvine(米国)
• [Int'l Joint Research] The University of New South Wales(オーストラリア)
• [Journal Article] Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA (2019)
  • Author(s): Shirakuni Seiya, Taniguchi Ittetsu, Tomiyama Hiroyuki
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: 12 Issue: 0 Pages: 42-45
  • DOI: 10.2197/ipsjtsldm.12.42
  • NAID: 130007603307
  • ISSN: 1882-6687
  • Peer Reviewed / Open Access
• [Journal Article] An OpenCL-based Software Framework for a Heterogeneous Multicore Architecture on Zynq-7000 SoC (2019)
  • Author(s): Miyazaki Takafumi, Takai Shunsuke, Taniguchi Ittetsu, Tomiyama Hiroyuki
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: 12 Issue: 0 Pages: 46-49
  • DOI: 10.2197/ipsjtsldm.12.46
  • NAID: 130007602929
  • ISSN: 1882-6687
  • Peer Reviewed / Open Access
• [Journal Article] A Branch-and-Bound Approach to Scheduling of Data-Parallel Tasks on Multicore Architectures (2019)
  • Author(s): Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: International Journal of Embedded Systems Volume: 印刷中
  • Peer Reviewed
• [Journal Article] ILP-based Scheduling for Malleable Fork-Join Tasks (2019)
  • Author(s): Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: ACM SIGBED Review Volume: 印刷中
  • Peer Reviewed
• [Journal Article] Energy-Aware Scheduling of Malleable Fork-Join Tasks under a Deadline Constraint on Heterogeneous Multicores (2019)
  • Author(s): Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: ACM SIGBED Review Volume: 印刷中
  • Peer Reviewed
• [Journal Article] A Constraint Programming Approach to Scheduling of Malleable Tasks (2019)
  • Author(s): Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: International Journal on Networking and Computing Volume: 印刷中
  • NAID: 130007680116
  • Peer Reviewed / Open Access
• [Journal Article] A Genetic Algorithm for Scheduling of Data-Parallel Tasks on Multicore Architectures (2019)
  • Author(s): Yang Liu, Lin Meng, Hiroyuki Tomiyama
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: 印刷中
  • NAID: 130007687122
  • Peer Reviewed / Open Access
• [Journal Article] Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures (2019)
  • Author(s): Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: 印刷中
  • NAID: 130007687116
  • Peer Reviewed / Open Access
• [Journal Article] A Dual-Mode Scheduling Approach for Task Graphs with Data Parallelism (2017)
  • Author(s): Yang Liu, Lin Meng, Ittetsu Taniguchi, and Hiroyuki Tomiyama
  • Journal Title: International Journal of Embedded Systems Volume: 9 Issue: 2 Pages: 147-156
  • DOI: 10.1504/ijes.2017.10004392
  • Peer Reviewed
• [Journal Article] A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers (2017)
  • Author(s): Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E100.A Issue: 7 Pages: 1496-1499
  • DOI: 10.1587/transfun.E100.A.1496
  • NAID: 130007311789
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed
• [Journal Article] Static Mapping of Parallelizable Tasks under Deadline Constraints (2017)
  • Author(s): Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E100.A Issue: 7 Pages: 1500-1502
  • DOI: 10.1587/transfun.E100.A.1500
  • NAID: 130007311788
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed
• [Journal Article] ILP-Based Scheduling for Parallelizable Tasks (2017)
  • Author(s): Kana Shimada, Shogo Kitano, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E100.A Issue: 7 Pages: 1503-1505
  • DOI: 10.1587/transfun.E100.A.1503
  • NAID: 130007311787
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed
• [Journal Article] Static Mapping of Multiple Parallel Applications on Non-Hierarchical Manycore Embedded Systems (2016)
  • Author(s): Yining Xu, Yang Liu, Junya Kaida, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E99.A Issue: 7 Pages: 1417-1419
  • DOI: 10.1587/transfun.E99.A.1417
  • NAID: 130005159605
  • ISSN: 0916-8508, 1745-1337
  • Peer Reviewed / Acknowledgement Compliant
• [Presentation] Communication-Aware Scheduling for Malleable Tasks (2019)
  • Author(s): Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Conference on Platform Technology and Service
  • Int'l Joint Research
• [Presentation] 近似乗算器の手書き文字認識CNNへの適用事例 (2019)
  • Author(s): 白根健太, 山元貴普, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/HWS研究会
• [Presentation] 高位合成における関数レベルのモジュール共有 (2019)
  • Author(s): 野崎竜平, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/HWS研究会
• [Presentation] SDSoCを用いたCHStoneベンチマークプログラムの高位合成 (2019)
  • Author(s): 足立卓哉, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/HWS研究会
• [Presentation] 分散かつ集中型メモリを有するFPGAメニーコアの設計 (2019)
  • Author(s): 白國誠也, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/HWS研究会
• [Presentation] RTOSを用いたシステムのフルハードウェア実装とその自動化 (2019)
  • Author(s): 大迫裕樹, 石浦菜岐佐, 冨山宏之, 神原弘之
  • Organizer: 電子情報通信学会VLD/HWS研究会
• [Presentation] High-Level Synthesis of the CHStone Benchmark Programs with SDSoC (2018)
  • Author(s): Takuya Adachi, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Taiwan and Japan Conference on Circuits and Systems
  • Int'l Joint Research
• [Presentation] Function-Level Module Sharing with High-Level Synthesis (2018)
  • Author(s): Ryohei Nozaki, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Taiwan and Japan Conference on Circuits and Systems
  • Int'l Joint Research
• [Presentation] A Systematic Approach to Design of Approximate Array Multipliers (2018)
  • Author(s): Takahiro Yamamoto, Kenta Shirane, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
  • Organizer: Taiwan and Japan Conference on Circuits and Systems
  • Int'l Joint Research
• [Presentation] Communication-Aware Scheduling of Data-Parallel Tasks (2018)
  • Author(s): Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
  • Int'l Joint Research
• [Presentation] Synthesis of Full Hardware Implementation of RTOS-Based Systems (2018)
  • Author(s): Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara
  • Organizer: International Symposium on Rapid System Prototyping
  • Int'l Joint Research
• [Presentation] Energy-Aware Scheduling of Malleable Fork-Join Tasks under a Deadline Constraint on Heterogeneous Multicores (2018)
  • Author(s): Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Embedded Operating System Workshop
  • Int'l Joint Research
• [Presentation] Scheduling of Malleable Tasks Based on Constraint Programming (2018)
  • Author(s): Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: IEEE Region 10 Conference
  • Int'l Joint Research
• [Presentation] Scheduling of Malleable Fork-Join Tasks with Constraint Programming (2018)
  • Author(s): Hiroki Nishikawa, Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Symposium on Computing and Networking
  • Int'l Joint Research
• [Presentation] A Case Study on Memory Architecture Exploration for Manycores on an FPGA (2018)
  • Author(s): Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Workshop on Computer Systems and Architectures
  • Int'l Joint Research
• [Presentation] Revisiting Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors (2018)
  • Author(s): Takafumi Miyazaki, Hayato Hidari, Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Workshop on Advances in Networking and Computing
  • Int'l Joint Research
• [Presentation] FPGA向けメニーコアのメモリアーキテクチャ探索の事例研究 (2018)
  • Author(s): 白國誠也, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/DC/情報処理学会SLDM/EMB研究会
• [Presentation] GPU向けOpenCLプログラムのマルチコア上での実行方式の改良 (2018)
  • Author(s): 宮崎貴史, 左隼人, 北條直久, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/DC/情報処理学会SLDM/EMB研究会
• [Presentation] 非均質マルチコアにおける可変並列度タスクの低消費エネルギー化スケジューリング (2018)
  • Author(s): 西川広記, 島田佳奈, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/DC/情報処理学会SLDM/EMB研究会
• [Presentation] 通信時間を考慮した並列タスクのスケジューリング (2018)
  • Author(s): 島田佳奈, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/DC/情報処理学会SLDM/EMB研究会
• [Presentation] A Heterogeneous Multicore Architecture and a Parallel Software Environment for Zynq SoC (2018)
  • Author(s): Takafumi Miyazaki, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Symposium on Advanced Technologies and Applications in the Internet of Things
  • Int'l Joint Research
• [Presentation] A Genetic Algorithm for Scheduling of Data-Parallel Tasks (2018)
  • Author(s): Yang Liu, Lin Meng, Hiroyuki Tomiyama
  • Organizer: International Symposium on Advanced Technologies and Applications in the Internet of Things
  • Int'l Joint Research
• [Presentation] Design of Asymmetric and Symmetric 32-core Architectures on FPGA (2018)
  • Author(s): Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Symposium on Advanced Technologies and Applications in the Internet of Things
  • Int'l Joint Research
• [Presentation] Malleable Task Scheduling with Constraint Programming (2018)
  • Author(s): 西川広記, 島田佳奈, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
• [Presentation] Zynq SoC向けヘテロジニアス・マルチコアと並列ソフトウェア環境の開発 (2018)
  • Author(s): 宮崎貴史, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
• [Presentation] 改良型配列型近似乗算器の設計と解析 (2017)
  • Author(s): 山元貴普, 谷口一徹, 冨山宏之, 山下茂, 原祐子
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2017-05-11
• [Presentation] An Empirical Study on Window Sizes in NLM-based Image Denoising (2017)
  • Author(s): Xiangbo Kong, 冨山宏之, 谷口一徹
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2017-05-11
• [Presentation] FPGA向け32コアアーキテクチャの設計 (2017)
  • Author(s): 白國誠也, 武苗棟之, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2017-05-11
• [Presentation] RTOSを用いたシステムの高位合成によるフルハードウェア化 (2017)
  • Author(s): 大迫裕樹, 石浦菜岐佐, 神原弘之, 冨山宏之
  • Organizer: 第19回組込みシステム技術に関するサマーワークショップ
• [Presentation] Binary Synthesis Implementing External Interrupt Handler as Independent Module (2017)
  • Author(s): Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama and Hiroyuki Kanbara
  • Organizer: International Symposium on Rapid System Prototyping
  • Int'l Joint Research
• [Presentation] Systematic Design of Approximate Array Multipliers with Different Accuracy (2017)
  • Author(s): Takahiro Yamamoto, Hiroyuki Tomiyama, Ittetsu Taniguchi, Shigeru Yamashita, Yuko Hara-Azumi
  • Organizer: International Workshop on Highly Efficient Neural Networks Design
  • Int'l Joint Research
• [Presentation] 可変な並列度を有するFork-Joinタスクのスケジューリング (2016)
  • Author(s): 島田佳奈, 谷口一徹, 冨山宏之
  • Organizer: 電子情報通信学会VLD/DC/情報処理学会SLDM研究会
  • Place of Presentation: 立命館大学大阪いばらきキャンパス（大阪府・茨木市）
  • Year and Date: 2016-11-28
• [Presentation] A Systematic Methodology for Design and Analysis of Approximate Array Multipliers (2016)
  • Author(s): Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi
  • Organizer: Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: Jeju (Korea)
  • Year and Date: 2016-10-27
  • Int'l Joint Research
• [Presentation] A Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks (2016)
  • Author(s): Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Workshop on Synthesis and System Integration of Mixed Information Technologies
  • Place of Presentation: 京都リサーチパーク（京都府・京都市）
  • Year and Date: 2016-10-24
  • Int'l Joint Research
• [Presentation] Analysis of Hierarchical 32-Core Architectures for FPGA-based Embedded Systems (2016)
  • Author(s): Seiya Shirakuni, Muneyuki Takenae, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Taiwan and Japan Conference on Circuits and Systems
  • Place of Presentation: Tainan (Taiwan)
  • Year and Date: 2016-08-01
  • Int'l Joint Research
• [Presentation] An OpenCL Framework for FPGA-based Heterogeneous Multicore Architecture (2016)
  • Author(s): Shunsuke Takai, Ittetsu Taniguchi, Hiroyuki Tomiyama, Sri Parameswaran
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: 沖縄県市町村自治会館（沖縄県・那覇市）
  • Year and Date: 2016-07-12
  • Int'l Joint Research
• [Presentation] ILP-based Scheduling for Malleable Parallel Tasks (2016)
  • Author(s): Kana Shimada, Shogo Kitano, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: 沖縄県市町村自治会館（沖縄県・那覇市）
  • Year and Date: 2016-07-12
  • Int'l Joint Research
• [Presentation] Deadline-Constrained Static Mapping of Parallelizable Tasks on Manycore Architectures (2016)
  • Author(s): Yining Xu, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: 沖縄県市町村自治会館（沖縄県・那覇市）
  • Year and Date: 2016-07-11
  • Int'l Joint Research
• [Presentation] マルチコア・タスクスケジューリング問題に対するモンテカルロ木探索の適用 (2016)
  • Author(s): 北野将梧, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-13
• [Presentation] GPU向けOpenCLプログラムのマルチコアプロセッサ上でのスレッド制御方式 (2016)
  • Author(s): 北條直久, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-13
• [Presentation] 並列化可能なリアルタイムタスクのメニーコアへの静的マッピング (2016)
  • Author(s): 徐亦檸, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-13
• [Presentation] 配列型近似乗算器の設計と解析 (2016)
  • Author(s): 山元貴普, 谷口一徹, 冨山宏之, 山下茂, 原祐子
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-13
• [Presentation] FPGAベースの組込みシステムを対象とした階層型マルチコア／メニーコアアーキテクチャの設計 (2016)
  • Author(s): 武苗棟之, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-12
• [Presentation] 整数計画法に基づく並列化可能タスクのスケジューリング (2016)
  • Author(s): 島田佳奈, 北野将梧, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-12
• [Presentation] FPGA上のヘテロジニアス・マルチコア向けOpenCL環境 (2016)
  • Author(s): 高井俊輔, 谷口一徹, 冨山宏之
  • Organizer: 回路とシステムワークショップ
  • Place of Presentation: 北九州国際会議場（福岡県・北九州市）
  • Year and Date: 2016-05-12
• [Presentation] A Case Study on Exploration of FPGA-based Multicore/Manycore Architectures (2016)
  • Author(s): Muneyuki Takenae, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Symposium on Low-Power and High-Speed Chips
  • Place of Presentation: 横浜情報文化センター（神奈川県・横浜市）
  • Year and Date: 2016-04-21
  • Int'l Joint Research
• [Presentation] 割込みハンドラを独立したモジュールとして実装するバイナリ合成 (2016)
  • Author(s): 伊藤直也, 石浦菜岐佐, 冨山宏之, 神原弘之
  • Organizer: 電子情報通信学会RECONF/CPSY/VLD/情報処理学会SLDM/ARC研究会
  • Place of Presentation: 慶応大学（神奈川県・横浜市）
  • Year and Date: 2016-01-21
• [Presentation] Comparison of Thread Execution Methods for GPU-oriented OpenCL Programs on Multicore Processors (2015)
  • Author(s): Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: Embedded Operating Systems Workshop
  • Place of Presentation: Amsterdam (Netherlands)
  • Year and Date: 2015-10-08
  • Int'l Joint Research
• [Presentation] Static Task Mapping for Non-Hierarchical Manycore SoCs (2015)
  • Author(s): Yining Xu, Junya Kaida, Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-07-01
  • Int'l Joint Research
• [Presentation] A Flexible Simulation Framework for Network-on-Chip with QEMU and SystemC (2015)
  • Author(s): Yusuke Fukutsuka, Yosuke Kurimoto, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-07-01
  • Int'l Joint Research
• [Presentation] Design and Implementation of Hierarchical 32-Core Architecture for FPGA-based Embedded Systems (2015)
  • Author(s): Muneyuki Takenae, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-06-30
  • Int'l Joint Research
• [Presentation] Revisiting Function Inlining in FPGA High-Level Synthesis (2015)
  • Author(s): Yohei Onishi, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-06-30
  • Int'l Joint Research
• [Presentation] Efficient Execution of OpenCL-based GPU Programs on Multicore Processors (2015)
  • Author(s): Naohisa Hojo, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-06-30
  • Int'l Joint Research
• [Presentation] A Lightweight OpenCL Framework for Embedded Multicore Processors (2015)
  • Author(s): Shunsuke Takai, Naoki Nishiyama, Ittetsu Taniguchi, Hiroyuki Tomiyama
  • Organizer: International Technical Conference on Circuits/Systems, Computers and Communications
  • Place of Presentation: Seoul (Korea)
  • Year and Date: 2015-06-30
  • Int'l Joint Research
• [Remarks] システムレベル設計方法論研究室
  • URL: http://www-ja.tomiyama-lab.org/