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Development of Next Generation Spectrometer for Radio Telescope

Research Project

Project/Area Number 15H05304
Research Category

Grant-in-Aid for Young Scientists (A)

Allocation TypeSingle-year Grants
Research Field Computer system
Research InstitutionTokyo Institute of Technology (2016-2018)
Ehime University (2015)

Principal Investigator

NAKAHARA HIROKI  東京工業大学, 工学院, 准教授 (20624414)

Project Period (FY) 2015-04-01 – 2019-03-31
Project Status Completed (Fiscal Year 2018)
Budget Amount *help
¥24,700,000 (Direct Cost: ¥19,000,000、Indirect Cost: ¥5,700,000)
Fiscal Year 2018: ¥2,990,000 (Direct Cost: ¥2,300,000、Indirect Cost: ¥690,000)
Fiscal Year 2017: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000)
Fiscal Year 2016: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2015: ¥16,900,000 (Direct Cost: ¥13,000,000、Indirect Cost: ¥3,900,000)
KeywordsFPGA / Radio Telescope / Digital Signal / Spectrometer / FFT / RNS / Deep Learning / CNN / 電波天文 / 分光器 / 深層学習 / 信号処理 / 計算機システム / 再構成可能LSI / Signal Processing / DSP
Outline of Final Research Achievements

We implemented an algorithm in which the operation order of spectrometers has been changed and an FFT circuit based on Residue Number System (RNS) is applied to the existing FPGA board (ROACH2 board), which is an existing facility. We compared it with the existing spectrometer released by CASPER (The Collaboration for Astronomy Signal Processing and Electronics Research). A 50 times wider and 2^16 points resolution spectrometer was realized by our development technologies. The data classifier after observation was realized for a CNN (Convolutional Neural Network). We reduced the size of CNN hardware by binary precision and sparse (Ternary, pruning zero weights) and clarified the practicability of FPGA implementation.

Academic Significance and Societal Importance of the Research Achievements

次世代電波望遠鏡用分光器を現行のROACH2 FPGAボード1台で実現できることができる. 本研究では, 提案回路の応用を電波望遠鏡としているが, ドップラー効果を利用した応用(CTスキャナ, 海洋レーダ, 気象レーダ等)に転用する事が可能となった.
また, 観測後のデータを要(測定対象)/不要に分類するDeep Learningの一種であるConvolutional Neural Network (CNN)のFPGA化に適したハードウェア削減・高速化手法を研究開発できたため, 帯域・実装コストの削減が可能となり, 監視カメラ・自動運転・ロボット・ドローン等へと適用可能となった.

Report

(5 results)
  • 2018 Annual Research Report   Final Research Report ( PDF )
  • 2017 Annual Research Report
  • 2016 Annual Research Report
  • 2015 Annual Research Report
  • Research Products

    (28 results)

All 2019 2018 2017 2016 2015 Other

All Journal Article (8 results) (of which Peer Reviewed: 8 results,  Acknowledgement Compliant: 4 results,  Open Access: 1 results) Presentation (19 results) (of which Int'l Joint Research: 19 results) Remarks (1 results)

  • [Journal Article] An FPGA Realization of a Random Forest with k-Means Clustering Using a High-Level Synthesis Design2018

    • Author(s)
      Akira Jinguji, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Transactions

      Volume: 101-D(2) Pages: 354-362

    • NAID

      130006328469

    • Related Report
      2018 Annual Research Report 2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA2018

    • Author(s)
      Tomoya Fujii, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Transactions

      Volume: 101-D(2) Pages: 376-386

    • NAID

      130006328491

    • Related Report
      2018 Annual Research Report 2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W2018

    • Author(s)
      Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
    • Journal Title

      IEEE Journal of Solid-State Circuits

      Volume: 53(4) Pages: 983-994

    • Related Report
      2017 Annual Research Report
    • Peer Reviewed
  • [Journal Article] LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification2016

    • Author(s)
      Hiroki Nakahara, Tsutomu Sasao, Hisashi Iwamoto, Munehiro Matsuura
    • Journal Title

      IEEE J. Emerg. Sel. Topics Circuits Syst.

      Volume: 6 Pages: 73-86

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)2016

    • Author(s)
      Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Hisashi Iwamoto
    • Journal Title

      Multiple-Valued Logic and Soft Computing

      Volume: 26 Pages: 109-123

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division2016

    • Author(s)
      Hiroki Nakahara, Hiroyuki Nakanishi, Kazumasa Iwai, Tsutomu Sasao
    • Journal Title

      SIGARCH Computer Architecture News

      Volume: 44 Pages: 44-49

    • Related Report
      2016 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] LUT cascades based on edge-valued multi-valued decision diagrams: Application to packet classification2016

    • Author(s)
      H. Nakahara, T. Sasao, H. Iwamoto, and M. Matsuura
    • Journal Title

      IEEE Journal on Emerging and Selected Topics in Circuits and Systems

      Volume: 6 Issue: 1 Pages: 73-86

    • DOI

      10.1109/jetcas.2016.2528638

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Journal Article] An Update Method for a Low Power CAM Emulator using an LUT Cascade Based on an EVMDD (k)2015

    • Author(s)
      H. Nakahara, T. Sasao, M. Matsuura, and H. Iwamoto
    • Journal Title

      Journal of Multiple-Valued Logic and Soft Computing

      Volume: 26 Pages: 109-123

    • Related Report
      2015 Annual Research Report
    • Peer Reviewed / Acknowledgement Compliant
  • [Presentation] Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation2019

    • Author(s)
      Masayuki Shimoda, Youki Sada, Hiroki Nakahara
    • Organizer
      ARC 2019
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FPGA-based Fine Tuning Accelerator for a Sparse CNN2019

    • Author(s)
      Hiroki Nakahara, Akira Jinguji, Masayuki Shimoda, Shimpei Sato
    • Organizer
      FPGA 2019
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA2018

    • Author(s)
      Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
    • Organizer
      FPGA 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Demonstration of FPGA-Based You Only Look Once Version2 (YOLOv2)2018

    • Author(s)
      Hiroki Nakahara, Masayuki Shimoda, Shimpei Sato
    • Organizer
      FPL 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Demonstration of Object Detection for Event-Driven Cameras on FPGAs and GPUs2018

    • Author(s)
      Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
    • Organizer
      FPL 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Power Efficient Object Detector with an Event-Driven Camera on an FPGA2018

    • Author(s)
      Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
    • Organizer
      HEART 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Performance Per Power Efficient Object Detector on an FPGA for Robot Operating System (ROS)2018

    • Author(s)
      Haoxuan Cheng, Shimpei Sato, Hiroki Nakahara
    • Organizer
      HEART 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector2018

    • Author(s)
      Hiroki Nakahara, Tsutomu Sasao
    • Organizer
      ISCAS 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Ternary Weight Binary Input Convolutional Neural Network: Realization on the Embedded Processor2018

    • Author(s)
      Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara
    • Organizer
      ISMVL 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications2018

    • Author(s)
      Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
    • Organizer
      VLSI Circuits 2018
    • Related Report
      2018 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGA2018

    • Author(s)
      Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato
    • Organizer
      FPGA
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A fully connected layer elimination for a binarizec convolutional neural network on an FPGA2017

    • Author(s)
      Hiroki Nakahara, Tomoya Fujii, Shimpei Sato
    • Organizer
      FPL
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGA2017

    • Author(s)
      Hiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato
    • Organizer
      FPT
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] On-Chip Memory Based Binarized Convolutional Deep Neural Network Applying Batch Normalization Free Technique on an FPGA2017

    • Author(s)
      Haruyoshi Yonekawa, Hiroki Nakahara
    • Organizer
      IPDPS Workshops
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Random Forest Using a Multi-valued Decision Diagram on an FPGA2017

    • Author(s)
      Hiroki Nakahara, Akira Jinguji, Simpei Sato, Tsutomu Sasao
    • Organizer
      ISMVL
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning2017

    • Author(s)
      Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
    • Organizer
      ARC
    • Related Report
      2017 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FFT Circuit Using Nested RNS in a Digital Spectrometer for a Radio Telescope2016

    • Author(s)
      Hiroki Nakahara, Tsutomu Sasao, Hiroyuki Nakanishi, Kazumasa Iwai, Tohru Nagao, Naoya Ogawa
    • Organizer
      International Symposium on Multiple-Valued Logic
    • Place of Presentation
      北海道(北海道大学)
    • Year and Date
      2016-05-18
    • Related Report
      2016 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A deep convolutional neural network based on nested residue number system2015

    • Author(s)
      H. Nakahara and T. Sasao
    • Organizer
      25th International Conference on Filed-Programmable Logic and Applications (FPL 2015)
    • Place of Presentation
      Royal Institution (London,England)
    • Year and Date
      2015-09-02
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An RNS FFT circuit using LUT cascades based on a modulo EVMDD2015

    • Author(s)
      H. Nakahara, T. Sasao, H. Nakanishi, and K. Iwai
    • Organizer
      The 45th IEEE International Symposium on Multiple-valued Logic (ISMVL 2015)
    • Place of Presentation
      University of Waterloo (Waterloo,Canada)
    • Year and Date
      2015-05-18
    • Related Report
      2015 Annual Research Report
    • Int'l Joint Research
  • [Remarks] 研究業績(中原啓貴)

    • URL

      http://www.hirokinakaharaoboe.net/publications_J.html

    • Related Report
      2015 Annual Research Report

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Published: 2015-04-16   Modified: 2020-03-30  

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