Write time reduction code for PRAM
| Project/Area Number |
15K00069
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Computer system
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| Research Institution | Chiba University |
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Principal Investigator |
Namba Kazuteru 千葉大学, 大学院工学研究院, 准教授 (60359594)
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| Co-Investigator(Kenkyū-buntansha) |
加藤 健太郎 鶴岡工業高等専門学校, 創造工学科, 准教授 (10569859)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2017: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2016: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2015: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | メモリシステム / PCM / 符号 / 書き込み時間削減 / 回路とシステム |
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| Outline of Final Research Achievements |
Our recent society is supported by information system, which is supported by computer system. Memory system is one of the most important parts of the computer system. The improvement of its performance is industrially important. Furthermore academic interest is also strong. In recent years, PRAM has attracted attention from many researchers and engineers as a new non-volatile memory. However, the PRAM has a considerable drawback; its write latency is not good. This work has presented a write latency reduction scheme which is better than the existing schemes.
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Report
(4 results)
Research Products
(4 results)
