| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2017: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2016: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2015: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
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| Outline of Final Research Achievements |
We studied layout design methods for superconducting single-flux-quantum logic circuits which can realize super high-speed and low-power consumption digital circuits. (1) We developed a channel routing method considering wire-length matching for precise adjustment of pulse arrival timing. (2) We proposed a new circuit design flow in which logic design and delay optimization are performed separately. In the logic design stage, we describe the circuit topology as well as the order of pulse arrival at each logic gate and the target operation frequency. In layout design, placement and routing are performed with minimizing circuit delay under the condition of the operation frequency. (3) We proposed usages of circuit design tools according to the design flow of (2), and developed related tools.
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