Development of Tamper-resistant Asynchronous Processors for Avoiding Information Leakage using Dynamic Analysis Methods
| Project/Area Number |
15K00179
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Research Field |
Information security
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| Research Institution | Hirosaki University |
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Principal Investigator |
Imai Masashi 弘前大学, 理工学研究科, 教授 (70323665)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2017: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2016: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2015: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Keywords | サイドチャネル攻撃 / 耐タンパ / 非同期式回路 / 2phaseハンドシェイクプロトコル / 束データ方式データ転送 / ランダム遅延素子 / 線形帰還シフトレジスタ / AES暗号化回路 / ハードウェアトロイ / セルライブラリ / 低ノイズ / 低電圧 |
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| Outline of Final Research Achievements |
Side-channel attacks have become one of serious issues in the modern VLSI systems. In asynchronous systems which do not require any clock signals, it is possible to change current/electromagnetic wave characteristics when performing the same logical operations by using random delay elements that can change the magnitude of their delay values at random. In this research, two-phase handshaking asynchronous circuits which do not distinguish between rising edges and falling edges are assumed in order to achieve high-performance circuits. The proposed random delay cells contain six inverter gates in which load capacitances are inserted into the second and the fifth inverter gates. The effectiveness of the proposed scheme is shown using asynchronous AES encryption circuits.
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Report
(4 results)
Research Products
(29 results)
