Study on fully digital ternary content addressable memory for high-speed processing of the big data.

• Project/Area Number: 15K06021
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Multi-year Fund
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: NAKAMURA KAZUYUKI 九州工業大学, マイクロ化総合技術センター, 教授 (60336097)
• Project Period (FY): 2015-10-21 – 2018-03-31
• Project Status: Completed (Fiscal Year 2017)
• Budget Amount: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000); Fiscal Year 2017: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2016: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000); Fiscal Year 2015: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
• Keywords: TCAM / SRAM / 素子劣化 / レシオレス / ばらつき / 動作マージン / 低電圧 / 連想メモリ / CAM / 低消費電力 / 検索 / ハードウエアエンジン / 超低電圧

Outline of Final Research Achievements

A fully digital ternary content addressable memory (TCAM) using the ratioless static random access memory (RL-SRAM) technology and fully complementary hierarchical-AND matching comparators (HAMCs) was developed. Since its fully complementary and digital operation enables the effect of device variabilities to be avoided, it can operate with a quite low supply voltage. A test chip incorporating a conventional TCAM and a proposed 24-transistor ratioless TCAM (RL-TCAM) cells and HAMCs was developed using a 0.18um CMOS process. The minimum operating voltage of 0.25V of the developed RL-TCAM is less than half of that of the conventional TCAM.

Research Products

• [Journal Article] Design and measurement of fully digital ternary content addressable memory using ratioless static random access memory cells and hierarchical-AND matching comparator (2018)
  • Author(s): D. Nishikata, M. A. Bin Mohd Ali, K. Hosoda, H.Matsumoto, K. Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: 57 Issue: 4S Pages: 04FF11-04FF11
  • DOI: 10.7567/jjap.57.04ff11
  • NAID: 120006778228
  • Peer Reviewed / Open Access / Int'l Joint Research
• [Journal Article] Self-stabilization techniques for intermediate power level in stacked-Vdd integrated circuits using DC-balanced coding methods (2016)
  • Author(s): Yusuke Kohara, Naoya Kubo, Tomofumi Nishiyama, Taiki Koizuka, Mohammad Alimudin, Amirul Rahmat, Hitoshi Okamura, Tomoyuki Yamanokuchi, Kazuyuki Nakamura
  • Journal Title: Japanese Journal of Applied Physics Volume: 55 Issue: 4S Pages: 04EF06-04EF06
  • DOI: 10.7567/jjap.55.04ef06
  • NAID: 210000146329
  • Peer Reviewed / Open Access / Acknowledgement Compliant
• [Presentation] Fully Digital Ternary Content Addressable Memory using Ratio-less SRAM Cells and Hierarchical-AND Matching Comparator for Ultra-low-voltage Operation (2017)
  • Author(s): D. Nishikata, M. A. Bin Mohd Ali, K. Hosoda, H.Matsumoto, K. Nakamura
  • Organizer: 2017 International Conference on Solid State Devices and Materials
  • Int'l Joint Research
• [Presentation] Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability (2017)
  • Author(s): S. Yamaguchi, H. Imi, S. Tokumaru, T Kondo, H. Yamamoto, K. Nakamura
  • Organizer: IEEE International Conference on Microelectronic Test Structures (ICMTS) 2017
  • Place of Presentation: Grenoble, FRANCE
  • Int'l Joint Research
• [Presentation] Vth-Shiftable SRAM Cell TEGs for Direct Measurement for the immunity of the Threshold Voltage Variability (2016)
  • Author(s): S. Yamaguchi, H. Imi, S. Tokumaru, K. Nakamura
  • Organizer: IEEE/ACM Workshop on Variability Modeling and Characterization
  • Place of Presentation: Austin,TX,USA
  • Int'l Joint Research
• [Patent(Industrial Property Rights)] 符号変換回路及び並列信号変換送受信システム (2016)
  • Inventor(s): 小原祐輔、久保直也、中村和之
  • Industrial Property Rights Holder: 小原祐輔、久保直也、中村和之
  • Industrial Property Rights Type: 特許
  • Industrial Property Number: 2016-053531
  • Filing Date: 2016-03-17