A Research on FPGA Accelerator for Large-Scale Applications
| Project/Area Number |
15K12001
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | University of Tsukuba |
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Principal Investigator |
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2017: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2015: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | FPGA / DRAM / ソーティング / 高速計算 / インタリーブ / 外部メモリ / 大規模問題 |
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| Outline of Final Research Achievements |
In this research, we propose an FPGA computational model for problems that require many off-chip memory accesses. In this model, (1) many threads are processed in parallel on the FPGA, (2) memory access from each thread is grouped dynamically according to its target memory bank number, (3) the memory interface achieves the maximum throughput by accessing the banks in turn, and (4) the fetched data are sent back to the thread that issued the request. We examined the effectiveness of this model through the evaluation of several real applications.
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Report
(4 results)
Research Products
(2 results)
