A Research on FPGA Accelerator for Large-Scale Applications

Research Project

Project/Area Number	15K12001
Research Category	Grant-in-Aid for Challenging Exploratory Research
Allocation Type	Multi-year Fund
Research Field	Computer system
Research Institution	University of Tsukuba
Principal Investigator	Tsutomu Maruyama 筑波大学, システム情報系, 教授 (00292532)
Project Period (FY)	2015-04-01 – 2018-03-31
Project Status	Completed (Fiscal Year 2017)
Budget Amount *help	¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000) Fiscal Year 2017: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000) Fiscal Year 2016: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000) Fiscal Year 2015: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Keywords	FPGA / DRAM / ソーティング / 高速計算 / インタリーブ / 外部メモリ / 大規模問題
Outline of Final Research Achievements	In this research, we propose an FPGA computational model for problems that require many off-chip memory accesses. In this model, (1) many threads are processed in parallel on the FPGA, (2) memory access from each thread is grouped dynamically according to its target memory bank number, (3) the memory interface achieves the maximum throughput by accessing the banks in turn, and (4) the fetched data are sent back to the thread that issued the request. We examined the effectiveness of this model through the evaluation of several real applications.

Report

(4 results)