| Project/Area Number |
15K12003
|
|---|
| Research Category |
Grant-in-Aid for Challenging Exploratory Research
|
| Allocation Type | Multi-year Fund |
|---|
| Research Field |
Computer system
|
|---|
| Research Institution | Kyushu Institute of Technology |
|---|
Principal Investigator |
Wen Xiaoqing 九州工業大学, 大学院情報工学研究院, 教授 (20250897)
|
|---|
| Co-Investigator(Kenkyū-buntansha) |
梶原 誠司 九州工業大学, 大学院情報工学研究院, 教授 (80252592)
宮瀬 紘平 九州工業大学, 大学院情報工学研究院, 准教授 (30452824)
Holst Stefan 九州工業大学, 大学院情報工学研究院, 助教 (40710322)
|
|---|
| Research Collaborator |
Chakravarty K.
Tehranipoor M.
Girard P.
Wunderlich H.-J.
HAMADA Shuji
Wang L.-T.
Jan M. E.
HADATE Koji
|
|---|
| Project Period (FY) |
2015-04-01 – 2018-03-31
|
| Project Status |
Completed (Fiscal Year 2017)
|
| Budget Amount *help |
¥3,380,000 (Direct Cost: ¥2,600,000、Indirect Cost: ¥780,000)
Fiscal Year 2017: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2016: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2015: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
|
|---|
| Keywords | LSI回路 / スキャンテスト / テスト電力 / シフト電力 / IR-Drop / クロック / シフトエラー / 誤テスト / LSIテスト / テスト電力制御 / 誤テスト回避 / 信号値遷移 / パス遅延 / クロックパス |
|---|
| Outline of Final Research Achievements |
This study points out that the root causes of false testing of low-power LSI circuits are (1) the unbalanced switching activity around clock trees for two adjacent flip-flops in a scan chain and (2) the excessive switching activity around long activated functional paths. From these unique observations, we propose a method called L-FTA: Layout-Level False Test Avoidance, which avoids possible false testing through sophisticated local layout adjustment for logic elements around clock trees and/or long sensitized functional paths. Extensive benchmark-circuit-based simulation and evaluation-based on test chips, the effectiveness of the proposed method has been confirmed. This novel high-quality LSI test technology is expected to significantly contribute to the creation of the next-generation low-power LSI cricuits.
|
