| Project/Area Number |
15K12005
|
|---|
| Research Category |
Grant-in-Aid for Challenging Exploratory Research
|
| Allocation Type | Multi-year Fund |
|---|
| Research Field |
Computer system
|
|---|
| Research Institution | National Institute of Informatics |
|---|
Principal Investigator |
Yoneda Tomohiro 国立情報学研究所, アーキテクチャ科学研究系, 教授 (30182851)
|
|---|
| Project Period (FY) |
2015-04-01 – 2018-03-31
|
| Project Status |
Completed (Fiscal Year 2017)
|
| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2016: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
|
|---|
| Keywords | 非同期式回路 / 遷移型 / 設計手法 / 新フリップフロップ / NoCルータ / 再構成可能デバイス / 再構成デバイス / Verilogシミュレーション |
|---|
| Outline of Final Research Achievements |
Transition signaling asynchronous circuits work based on the transitions of request and acknowledgement signals. Such a design methodology has potential to implement high performance circuits, but also requires specialized design techniques, which has prevented this approach from becoming popular among designers. In this research project, we utilize new and special flip-flops that have multiple clock inputs for the same outputs, and we provide new design method based on templates using them, in order to make it possible for even designers without specialized design techniques to easily implement transition signaling asynchronous circuits. An asynchronous NoC router has been designed for demonstrating the proposed method. Furthermore, this idea has been extended to an asynchronous reconfigurable device that contains those special flip-flops in a configurable logic block. Its naive version has been evaluated by simulation, and we have concluded that such an approach is promising.
|
