| Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2017: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2015: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
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| Outline of Final Research Achievements |
In this work, we explored latency hiding oriented description methods that not only achieve high performance but also facilitate complicated parallel programming for parallel computers equipped with accelerators such as the graphics processing unit (GPU). In more detail, we developed a data decomposition method and a performance model required for two program description schemes: one extends a GPU-based scheme for inter-node program description and the other extends an inter-node scheme for GPU program description. The effectiveness of the proposed methods was evaluated on multi-GPU systems with practical applications such as stencil computation.
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