Integrated-circuit implementation of chaotic Boltzmann machines for deep learning hardware

• Project/Area Number: 15K12110
• Research Category: Grant-in-Aid for Challenging Exploratory Research
• Allocation Type: Multi-year Fund
• Research Field: Soft computing
• Research Institution: Kyushu Institute of Technology
• Principal Investigator: Morie Takashi 九州工業大学, 大学院生命体工学研究科, 教授 (20294530)
• Co-Investigator(Kenkyū-buntansha): 鈴木 秀幸 大阪大学, 情報科学研究科, 教授 (60334257) ; 田向 権 九州工業大学, 大学院生命体工学研究科, 准教授 (90432955)
• Research Collaborator: YAMAGUCHI Masatoshi 九州工業大学, 大学院生命体工学研究科 ; KATO Takashi 九州工業大学, 大学院生命体工学研究科 ; WANG Quan 九州工業大学, 大学院生命体工学研究科 ; UENOHARA Seiji 九州工業大学, 大学院生命体工学研究科 ; KAWASHIMA Ichiro 九州工業大学, 大学院生命体工学研究科
• Project Period (FY): 2015-04-01 – 2017-03-31
• Project Status: Completed (Fiscal Year 2016)
• Budget Amount: ¥3,510,000 (Direct Cost: ¥2,700,000、Indirect Cost: ¥810,000); Fiscal Year 2016: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000); Fiscal Year 2015: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
• Keywords: ソフトコンピューティング / ニューラルネットワーク / 電子デバイス・機器 / 集積回路 / 深層学習 / 機械学習 / カオスボルツマンマシン

Outline of Final Research Achievements

Boltzmann machines are an important stochastic model in machine learning, and a chaotic Boltzmann machine (CBM) model has been proposed using deterministic chaos. We have implemented this model by both analog and digital integrated circuits (ICs), evaluated their performance, and developed the circuit design technology that can be applied to deep-learning hardware. We have implemented an exponential function used in the CBM model by the characteristics of the subthreshold region of a MOSFET in analog ICs, and by bit shift operation in digital ICs, and verified the operation of CBMs using real IC chips. We have designed a 100-neuron CBM in a digital IC, applied it to max-cut problems, and verified the output of the optimum solutions.

Research Products

• [Journal Article] A CMOS Chaotic Boltzmann Machine Circuit and Three-neuron Network Operation (2017)
  • Author(s): M. Yamaguchi, H. Tamukoh, H. Suzuki, and T. Morie
  • Journal Title: Proc. of Int. Joint Conf. on Neural Networks Volume: －
  • Peer Reviewed / Acknowledgement Compliant
• [Journal Article] Analog VLSI Circuits and Devices for Neuro-Inspired Time-Domain Computing (2016)
  • Author(s): T. Morie
  • Journal Title: Ext. Abstracts of Int. Conf. on Solid State Devices and Materials Volume: － Pages: 117-118
  • Peer Reviewed
• [Journal Article] Hardware-oriented Algorithm for Chaotic Boltzmann Machines (2016)
  • Author(s): I. Kawashima, S. Uenohara, T. Kato, M. Yamaguchi, H. Suzuki, T. Morie, and H. Tamukoh
  • Journal Title: Proc. of Int. Workshop on Smart Info-Media Systems in Asia Volume: － Pages: 122-125
  • Peer Reviewed / Acknowledgement Compliant
• [Journal Article] A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines (2016)
  • Author(s): M. Yamaguchi, T. Kato, Q. Wang, H. Suzuki, H. Tamukoh, and T. Morie
  • Journal Title: Proc. 23rd Int. Conf. on Neural Information Processing (ICONIP2016) Volume: 9947 Pages: 248-255
  • DOI: 10.1007/978-3-319-46687-3_27
  • ISBN: 9783319466866, 9783319466873
  • Peer Reviewed / Acknowledgement Compliant
• [Presentation] A CMOS Chaotic Boltzmann Machine Circuit and Three-neuron Network Operation (2017)
  • Author(s): M. Yamaguchi, H. Tamukoh, H. Suzuki, and T. Morie
  • Organizer: Int. Joint Conf. on Neural Networks
  • Place of Presentation: Anchorage, USA
  • Year and Date: 2017-05-15
  • Int'l Joint Research
• [Presentation] カオスボルツマンマシンのアナログ集積回路実装 (2017)
  • Author(s): 山口正登志, 田向 権, 鈴木 秀幸, 森江 隆
  • Organizer: 電子情報通信学会 総合大会
  • Place of Presentation: 名古屋
  • Year and Date: 2017-03-22
• [Presentation] Analog CMOS VLSI Implementation of Chaotic Boltzmann Machines (2017)
  • Author(s): M. Yamaguchi, H. Tamukoh, H. Suzuki, and T. Morie
  • Organizer: The 5th RIEC Int. Symp. on Brain Functions and Brain Computer
  • Place of Presentation: Sendai, Japan
  • Year and Date: 2017-02-27
  • Int'l Joint Research
• [Presentation] A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines (2016)
  • Author(s): M. Yamaguchi, T. Kato, Q. Wang, H. Suzuki, H. Tamukoh, and T. Morie
  • Organizer: Int. Conf. on Neural Information Processing
  • Place of Presentation: Kyoto, Japan
  • Year and Date: 2016-10-17
  • Int'l Joint Research
• [Presentation] Analog VLSI Circuits and Devices for Neuro-Inspired Time-Domain (2016)
  • Author(s): T. Morie
  • Organizer: Int. Conf. on Solid State Devices and Materials
  • Place of Presentation: Tsukuba, Japan
  • Year and Date: 2016-09-29
  • Int'l Joint Research / Invited
• [Presentation] Hardware-oriented Algorithm for Chaotic Boltzmann Machines (2016)
  • Author(s): I. Kawashima, S. Uenohara, T. Kato, M. Yamaguchi, H. Suzuki, T. Morie, and H. Tamukoh
  • Organizer: Int. Workshop on Smart Info-Media Systems in Asia
  • Place of Presentation: Ayutthaya, Thailand
  • Year and Date: 2016-09-15
  • Int'l Joint Research
• [Presentation] カオスボルツマンマシンのディジタルハードウェア実装に関する検討 (2016)
  • Author(s): 川島 一朗, 上ノ原 誠二, 加藤 孝史, 山口 正登志, 鈴木 秀幸, 森江 隆, 田向 権
  • Organizer: 電子情報通信学会 総合大会
  • Place of Presentation: 九州大学伊都キャンパス（福岡）
  • Year and Date: 2016-03-16
• [Presentation] Software Simulation of Chaotic Boltzmann Machines (2015)
  • Author(s): Q. Wang, T. Kato, H. Suzuki, H. Tamukoh, and T. Morie
  • Organizer: 3rd Int. Symp. on Applied Engineering and Sciences (SAES2015)
  • Place of Presentation: Selangor, Malaysia
  • Year and Date: 2015-11-23
  • Int'l Joint Research
• [Presentation] カオスボルツマンマシンのCMOS回路化 (2015)
  • Author(s): 加藤 孝史, 上ノ原 誠二, 鈴木 秀幸, 田向 権, 森江 隆
  • Organizer: 電子情報通信学会 基礎・境界ソサイエティ大会
  • Place of Presentation: 東北大学（仙台市）
  • Year and Date: 2015-09-11
• [Presentation] 乱数生成不要なカオスボルツマンマシン回路 (2015)
  • Author(s): 加藤 孝史, 森江 隆
  • Organizer: VDECデザイナーズフォーラム 2015
  • Place of Presentation: 山代温泉（石川県）
  • Year and Date: 2015-08-29
• [Remarks] 九州工業大学 大学院生命体工学研究科 人間知能システム工学専攻 脳型集積システム研究室
  • URL: http://www.brain.kyutech.ac.jp/~morie/