| Project/Area Number |
15K13962
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| Research Category |
Grant-in-Aid for Challenging Exploratory Research
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| Allocation Type | Multi-year Fund |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku University |
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Principal Investigator |
Kotani Koji 東北大学, 工学研究科, 准教授 (20250699)
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| Project Period (FY) |
2015-04-01 – 2017-03-31
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| Project Status |
Completed (Fiscal Year 2016)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2016: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2015: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | 疑似三次元集積 / 集積回路 / 時間軸配線 / 時間軸 / 擬似三次元集積 |
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| Outline of Final Research Achievements |
In this study, as a novel integrated circuit architecture, a quasi-3D integration scheme, in which time domain is taken as a new integration dimension and combined with a conventional physical 2D integration of the integrated circuit technology, has been established and its effectiveness has been evaluated. Taking multiple-stage 2D image processing circuits as a specific evaluation example, a quasi-3D signal processing architecture composed of an array of unit processing nodes and temporary memory elements acting as time-domain interconnects has been developed. Its superior performance against the conventional parallel processing architecture, in which multiple signal processing layers are simply placed in a 2D integration plane, has been demonstrated.
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