| Project/Area Number |
15K15960
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Multi-year Fund |
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| Research Field |
Computer system
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| Research Institution | Nara Institute of Science and Technology (2017)
Kyoto University (2015-2016) |
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Principal Investigator |
Shintani Michihiro 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (80748913)
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| Project Period (FY) |
2015-04-01 – 2018-03-31
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| Project Status |
Completed (Fiscal Year 2017)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2017: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
Fiscal Year 2016: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2015: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
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| Keywords | トランジスタ / MOSFET / プロセッサ設計 / 経年劣化 / NBTI / タイミング解析 / 回路シミュレーション / NBTI緩和 |
|---|
| Outline of Final Research Achievements |
Integrated circuits are now indispensable components of infrastructures to improve quality of our life with advancements of semiconductor technology scaling. On the other hand, the performance of MOS transistors, which is major component of the circuits, is known to severely degrade with time as they are stressed. Among numerous degradation phenomena, this study focuses on bias temperature stability (NBTI: Negative bias temperature instability). By proposing NBTI deterioration modeling method, NBTI-induced path Delay degradation estimation method, and degradation mitigation method, we improve the reliability of large-scale circuits, such as microprocessors.
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