| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2017: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2016: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2015: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
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| Outline of Final Research Achievements |
In this study we proposed a scheme to detect transient faults occurring in logic circuits, which are caused by switching noises of DC-AC inverters. We introduce dual approximate logic, which combines the concepts of approximate logic that is partially equivalent to the original circuit, and of dual logic. We used simulations for small benchmark and sample circuits to evaluate the effectiveness of the proposed scheme in terms of detection capability.
We also studied fast test pattern generation based on critical area, in order to specify and test target circuit which is protected by dual approximated logic. By combining 2-step test generation and window-based searching, the proposed scheme achieved 40% of pattern count reduction, as well as 10x speed-up.
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