| Project/Area Number |
16206034
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| Research Category |
Grant-in-Aid for Scientific Research (A)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tokyo Institute of Technology |
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Principal Investigator |
MASU Kazuya Tokyo Institute of Technology, Integrated Research Institute, Professor (20157192)
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| Co-Investigator(Kenkyū-buntansha) |
ITO Hiroyuki Tokyo Institute of Technology, Precision and Intelligent Laboratory, Assistant Professor (40451992)
SATO Takashi Tokyo Institute of Technology, Integrated Research Institute, Professor (20431992)
AMAKAWA Shuhei Tokyo Institute of Technology, Integrated Research Institute, Assistant Professor (40431994)
ISHIDA Koichi Tokyo Institute of Technology, Integrated Research Institute, Assistant Professor (30431993)
岡田 健一 東京工業大学, 統合研究院, 助手 (70361772)
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| Project Period (FY) |
2004 – 2007
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| Project Status |
Completed (Fiscal Year 2007)
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| Budget Amount *help |
¥49,790,000 (Direct Cost: ¥38,300,000、Indirect Cost: ¥11,490,000)
Fiscal Year 2007: ¥9,100,000 (Direct Cost: ¥7,000,000、Indirect Cost: ¥2,100,000)
Fiscal Year 2006: ¥10,530,000 (Direct Cost: ¥8,100,000、Indirect Cost: ¥2,430,000)
Fiscal Year 2005: ¥13,260,000 (Direct Cost: ¥10,200,000、Indirect Cost: ¥3,060,000)
Fiscal Year 2004: ¥16,900,000 (Direct Cost: ¥13,000,000、Indirect Cost: ¥3,900,000)
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| Keywords | transmission line / integrated cirtcuit / nano interconnect / high speed signal propagation / low power consumption / system on chip / network on chip / wire length distribution |
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| Research Abstract |
Si CMOS has been scaled according to the "Scaling Concept" and have achieved high performance, low power consumption, and high functionality. The Si CMOS has become the most important hardware in ubiquitous network. In 2013, hundred million transistors will be integrated on a one chip of 20mm square using 35nm technology and the operating frequency is expected to be over 20GHz. The Si CMOS is progressing toward Nano Scale era.
In this work, the signal propagation is recognized to be just communication, and we have developed global wiring technology. The novel analytic expression has been derived for wire length distribution ; the wire length distribution and cumulative number of interconnects of real 130nm and 90nm CMOS chip are well expressed by our new model. We have developed global wiring technology based on differential transmission line ; 0.27pJ/bit transmission has been successfully achieved on 1cm long interconnect, and mutli drop transmission line interconnect has been also developed for future network on-chip technology. Furthermore, novel FoM (Figure of Merit) has been proposed to compare the performance of various interconnects ; the conventional RC line, the RC line using CNT (Carbon Nano Tube), transmission line interconnect which has been developed in this work, optical interconnect, and wireless interconnect. As a results, the FoM of the transmission line interconnect has most superior in the range of several hundred micron to several mm. This means the transmission line has been the best solution for global wiring.
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