| Project/Area Number |
16300019
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | KYUSHU UNIVERCITY (2005-2006)
Kyushu Institute of Technology (2004) |
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Principal Investigator |
SATO Toshinori Kyushu University, System LSI Research Center, Professor, システムLSI研究センター, 教授 (00322298)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥8,000,000 (Direct Cost: ¥8,000,000)
Fiscal Year 2006: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 2005: ¥2,700,000 (Direct Cost: ¥2,700,000)
Fiscal Year 2004: ¥3,200,000 (Direct Cost: ¥3,200,000)
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| Keywords | Energy efficiency / Low power / Systems on chip / Computer system / マイクロプロセッサ / 命令レベル並列処理 / 省電力 / クリティカルパス予測 |
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| Research Abstract |
Power consumption is a major concern in embedded microprocessors design. Reducing power has also been a critical design goal for general-purpose microprocessors. Since they require high performance as well as low power, power reduction at the cost of performance cannot be accepted. There are a lot of device-level techniques that reduce power with maintaining performance. They select non-critical paths as candidates for low-power design, and performance-oriented design is used only in speed-critical paths. The same philosophy can be applied to architectural-level design. We evaluate a technique, which exploits dynamic information regarding instruction criticality in order to reduce power. We evaluate an instruction steering policy for a clustered microarchitecture, which is based on instruction criticality, and find it is substantially energy-efficient while it suffers performance degradation.
In the deep submicron (DSM) semiconductor technologies, a conservative approach called "worst-case design" will not work very soon. The DSM increases noise and process variations and requires supply voltage reduction, and thus reduces design margins that worst-case design methodologies require. We have to design microprocessors by considering typical case rather than worst case. The Constructive Timing Violation (CTV) paradigm is such a design methodology, where designers are focusing on typical cases rather than worrying about very rare worst cases. We have designed two types of ALUs that utilize the CTV, each of which has its own problems in size and in speed. In order to solve the problems, we propose to utilize an adder-comparator as the fault detection circuit. Using Verilog-HDL, we implement a carry select adder that utilizes the CTV, and evaluate it on logic simulations after logic synthesis with delay information. It is observed that substaintial improvement in energy efficiency is achieved.
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