| Co-Investigator(Kenkyū-buntansha) |
EDA Hiroshi Ibaraki University, College of Engineering, Prof., 工学部, 教授 (60007995)
SHIMIZU Jun Ibaraki University, College of Engineering, Lecturer, 工学部, 講師 (40292479)
OJIMA Hirotaka Ibaraki University, College of Engineering, Research Associate, 工学部, 助手 (90375361)
仇 中軍 茨城大学, 理工学研究科・SVBL, 非常勤研究員
木村 俊一郎 (株)東京ダイヤモンド工具製作所, 技術部・研究員
神谷 純生 トヨタ自動車(株), 第2機能材料部, 担当部長(研究職)
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| Budget Amount *help |
¥14,600,000 (Direct Cost: ¥14,600,000)
Fiscal Year 2006: ¥4,200,000 (Direct Cost: ¥4,200,000)
Fiscal Year 2005: ¥4,300,000 (Direct Cost: ¥4,300,000)
Fiscal Year 2004: ¥6,100,000 (Direct Cost: ¥6,100,000)
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| Research Abstract |
After long term research and development, new energy sources like fuel cell, solar-electric power generation and wind force power generation are getting into the stage of practical use. The most essential driving force and enabling technology is the power electronics. Improvement in performance, function, reliability and miniaturization of power devices is increasingly demanded. Especially, the Field-Stop type IGBT (Insulated Gate Bipolar Transistor) is expected to make a technological break-through. Unlike the structure of conventional transistors, IGBT functions as the current flows across the thickness directions of the Si substrate. Since the switching resistance of IGBT is proportional to the thickness of the Si substrate, the current Punch-Through type IGBT is 350 μm thick and thus has a large energy loss. The problems encountered are the voltage drop and internal heat generation. The design for next-generation non-punch through type IGBT is 100 μm thick for automotive industry.
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Therefore, the Si wafer has to be thinned down to the diminished thickness.
In addition, the miniaturization and high degree integration of system LSI (large scale integrated) circuit are increasingly demanded by mobile devices. As a cost effective solution, low-profile-package containing multi-layer chips is applied into the products like IC cards, mobile phones and digital music players. The Si wafers have to be thinned down to 50〜70 μm from 725μm for 8 inch wafer or from 800μm for 12 inch wafer, before being diced into individual chips. At the next stage when the new transfixed interconnection technology is available, the wafer thickness required is further down to 30〜50 μm.
Backgrinding is the conventional method for reducing wafer to a diminished thickness suitable for the final packaging. The diamond wheels and process parameters are necessarily optimized to obtain minimal subsurface damage in grinding process. By use of the latest technologies in ultra precision engineering and the concept of ductile mode-machining, it is now able to control the cutting depth of each abrasive not to exceed the critical limit which causes the material fracture so that no crack remains on the surface after grinding. However, subsurface damage including plastic flow and residual stress are developed on the surface instead. As such kinds of defect degrade the wafer deflective strength, it is very difficult to thin wafer down below 150μm.
In order to remove such defects, a further smaller processing unit, in which the interactive force/energy is small enough not to cause silicon plastic deformation, is preferable. Polishing is an available technology possible to produce a surface almost free of plastic flow, but this sacrifices the geometric accuracy. As an alternative solution, a fixed abrasive process offers better accuracy in geometry, requires fewer steps of the equipment/process and discharges less waste disposal. However, the damaged layer of several μm to several ten μm thick is the barrier to the use fixed abrasive technology, as it is intolerable for Si substrates as typical ICs are built in the layer of 2〜10 μm thick from the topmost surface. To achieve a defect-free surface by fixed abrasive only, this research has successfully developed a novel chemo-mechanical-grinding (CMG) process, by introducing chemical effect into the grinding process. The results achieved during the period of this project are summarized as follows;
・A new grinding wheel which possesses solid-state chemical reaction with Si has been successfully developed.
・With above CMG wheel, it is able generate a defect free surface on the Φ300 mm Si wafer at a dry condition.
・The surface integrity of CMG is equivalent or better than that of commercial CMP wafer.
・A on-machine instrument has been successfully developed to measure the geometry of ground wafers.
・With the above instrument, it is able to get the 3 dimensional parameters including SFQR, GBIR, TTV and other geometric dimension necessary for control and evaluation of grinding operation.
・A molecular dynamic simulation has been performed to verify the CMG mechanism.
・The simulation results has revealed that the chemical aspect of CMG is based on the thermal-chemical reaction between Si and O_2, and the solid-state reaction between the CeO_2 abrasive and products of SiO_2, which forms a soft product in an amorphous complex and can be mechanically removed by relatively soft abrasives.
・The final thickness of CMG wafer is 30 μm for 8 inch wafers and 100 μm for 12 inch wafers, and the TTV is within 0.2% of the final thickness.
・The machining time including CMG is about 10 minutes for 8 inch wafers and 30 minutes for 12 inch wafers. Less
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