Development of Self Aligned Fabrication Process of High-Permittivity Gate Insulating Film for Low Consumption LSI
| Project/Area Number |
16360156
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | KYUSHU UNIVERSITY |
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Principal Investigator |
NAKASHIMA Hiroshi KYUSHU UNIVERSITY, Art, Science and Technology Center for Cooperative Research, Professor, 産学連携センター, 教授 (70172301)
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| Co-Investigator(Kenkyū-buntansha) |
NAKASHIMA Hideharu KYUSHU UNIVERSITY, Interdisciplinary Graduate School of Engineering Sciences, 大学院・総合理工学研究院, 教授 (80180280)
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| Project Period (FY) |
2004 – 2005
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| Project Status |
Completed (Fiscal Year 2005)
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| Budget Amount *help |
¥15,500,000 (Direct Cost: ¥15,500,000)
Fiscal Year 2005: ¥3,100,000 (Direct Cost: ¥3,100,000)
Fiscal Year 2004: ¥12,400,000 (Direct Cost: ¥12,400,000)
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| Keywords | Silicon / High permittivity insulating film / Electron cyclotron resonance plasma / High-k film / Silicon oxide film / Low consumption LSI / Hf Oxide Film / 窒化膜 |
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| Research Abstract |
This subject aims to establish the self-aligned process for high permittivity films having the SiO_2 equivalent oxide thickness (EOT) of less than 1.0 nm, which is fabricated by the plasma oxidation, Hf metal deposition, and oxidation of Hf metal using electron cyclotron resonance (ECR) plasma and followed by the post deposition anneals by the precise control of oxygen. The target of this study is to embody the high-k film of which the leak current is four orders of magnitude lower than that of SiO_2 and also the interface property is similar to that of SiO_2. The obtained results are summarized as follows :
1.1.2 nm thick SiO_2 fabrication by Ar/O_2 mixed plasma (optimum condition : O_2/Ar=0.1/30 scccm), 3 nm thick Hf metal deposition by ECR sputtering, and subsequent oxidation of Hf metal were carried out in the chamber without breaking vacuum, which was followed by rapid thermal anneal. The lowest EOT of 1.1 nm was obtained for the Hf oxidation of 8.5 min and the annealing of 650℃ fo
… More
r 30 s, in which the leak current density was four orders of magnitude lower than that of SiO_2. According to XPS measurements, it was found that the deposited HfO_x changes to HfO_2 and simultaneously the decrease of SiO_2 thickness and the formation of Hf silicate occur by the reaction of SiO_2 with Hf.
2.In order to use the TaN film for the gate metal of MOSFET, the TaN film was deposited by magnetron sputtering and optimized by the subsequent annealing. It was found that the TaN film enable us to use the processing at temperatures less than 750℃ in MOSFET fabrication. The etching of the TaN film was successfully established by the wet chemical etching with the Hf metal mask, leading to the MOSFET fabrication having channel length of 5 μm.
3.The fabrication process for metal-gate/high-k/Si-MOSFET was well established, which was employed TaN as metal gate and Hf oxide as high-k insulating film. The MOSFET showed the 40% increment of the performance, compared with that of SiO_2 having the same physical thickness as high-k film. Less
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Report
(3 results)
Research Products
(13 results)
