| Budget Amount *help |
¥10,700,000 (Direct Cost: ¥10,700,000)
Fiscal Year 2005: ¥2,100,000 (Direct Cost: ¥2,100,000)
Fiscal Year 2004: ¥8,600,000 (Direct Cost: ¥8,600,000)
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| Research Abstract |
For scaling of flash memory, the device having a few numbers of floating nanometer-scale dot has been proposed. The purpose of this study is to fabricate the flash memory having a few numbers of floating nanometer-scale dot with precise control of the number, position, and size by using electron beam (EB) lithography, and examine the channel conduction mechanism of carrier and retention mechanism, for clarify the scaling limit of the device. Also, another purpose is to use atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time.
For the purpose, we fabricated a few number of floating dot on the Si narrow channel or Si plane channel by using the EB lithography and dry and wet etchings, and investigated the electrical characteristics with systematically changing the number, size of the dot and the distance between the adjacent dots. By comparing the electrical characteristics of the device with and without the floating dots, we confirmed that the device with floating dots indeed realizes a memory operation at room temperature. By estimating the amount of the hysteresis of the device as a function of the dot number, we found that the amount of the hysteresis increases with the dot number along the channel. However, the hysteresis has no correlation with the number of the dot along the width of the channel. If the dot number is large, the retention time will not be shorten even when some of the dots have a leakage. Therefore, taking the retention time into account, increasing the dot number along the channel is important for improving the memory characteristics.
As to the usage of atomic-layer-deposited tunnel gate dielectrics for the improvement of retention time and right/erase time, we could not carried out. Therefore, we will do this in future.
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