Evaluation of Asynchronous Hardware in terms of Resistivity against Cryptographic Attacks and Optimum Implementation of IPSecurity
Grant-in-Aid for Scientific Research (C)
|Allocation Type||Single-year Grants |
|Research Institution||The University of Electro-Communications |
ABE Koki UEC, Faculty of Electro-Communications, Associate Professor, 電気通信学部, 助教授 (00017443)
|Project Period (FY)
2004 – 2005
Completed(Fiscal Year 2005)
|Budget Amount *help
¥3,700,000 (Direct Cost : ¥3,700,000)
Fiscal Year 2005 : ¥2,000,000 (Direct Cost : ¥2,000,000)
Fiscal Year 2004 : ¥1,700,000 (Direct Cost : ¥1,700,000)
|Keywords||cryptosystem implementation / differential power analysis / asynchronous hardware / bundled-data type / security protocol / VPN / 電力差分解析 / 消費電力モデル / 非同期回路 / ハンドシェイクプロトコル|
Attacks to cryptosystems called DPAs (Differential Power Attacks) that enable them to decode the secret information of the systems by observing time dependence of power consumption during executing encryption and decryption processes pose a serious treat to security using secret keys. For hardware design, asynchronous methodology is known in which a unique global clock is not used. In asynchronous devices, processing time varies according to types of operations and data. Thus the asynchronously designed cryptosystems are expected to have high resistivity against DPA. This study was aimed at realization of such security processing that disables decoding secret keys at low cost and with high performance. Its application to real world is another objective. Results achieved by this study are summarized as follows.
1.Developing methodology to evaluate DPA resistivity of cryptosystems : For designing secure cryptographic devices, evaluation of resistivity against attacks at each stage of desi
gn flow from front to back ends are needed. For front-end design we proposed and evaluated a high speed simulation method at algorithmic level. We found that for back-end design circuit simulations are effective.
2.Designing high speed and low cost asynchronous devices with low overhead : A new handshake protocol for bundled-data asynchronous circuits which can use the same data paths as those designed for synchronous circuits was proposed and implemented. The protocol generates efficiently stage delays. Evaluation experiments revealed that circuits implementing the protocol have lower power consumption and higher speed than conventional design.
3.Proposing effective DPA attacks and developing the countermeasures : Taking DES as an example, we proposed effective DPA attacks by properly selecting reference positions and bits as well as stochastic methods to process the sampled data. We also proposed a method to introduce random variables to encryption table called RST (Random Switching Table). RST is applicable to cryptosystems with macro memory in FPGA, and thus valuable in many real applications. Bundled-data asynchronous circuits with RST for data paths are expected to improve all aspects of speed, power consumption, and security.
4.Evaluating performance of VPN (Virtual Private Network) as an application of security protocol : We focused on OpenVPN as a representative of open source VPN software and evaluated the performance. Results showed that cache can form a bottleneck in software implementation of VPN. In such applications, dedicated hardware will be effective, and hardware cryptosystems with DPA resistivity will increase the degree of security, which belong to future work.
Achievements of the research have been published in 29 articles (2 Japanese journals, 4 English journals, 5 international conference proceedings, and 18 domestic conference proceedings). An application of patent was made based on results from related study. Less
Research Products (77results)