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Study on LSI testing for multiple fault models

Research Project

Project/Area Number 16500036
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionKyushu Institute of Technology

Principal Investigator

KAJIHARA Seiji  Kyushu Institute of Technology, Faculty of Computer Science and Systems Engineering, Professor, 情報工学部, 教授 (80252592)

Co-Investigator(Kenkyū-buntansha) WEN Xiaoqing  Kyushu Institute of Technology, Graduate School of Computer Science and Systems Engineering, Associate Professor, 大学院情報工学研究科, 助教授 (20250897)
Project Period (FY) 2004 – 2006
Project Status Completed (Fiscal Year 2006)
Budget Amount *help
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2006: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 2005: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2004: ¥1,900,000 (Direct Cost: ¥1,900,000)
Keywordsdesign and test of LSIs / logic circuit / test pattern generation / fault diagnosis / bridging fault / delay fault / dependability / fault simulation / テスト生成 / システムオンチップ / 計算機システム / ディペンダブル・コンピューティング / X故障モデル / N回検出テスト
Research Abstract

With the progress of design and manufacturing technology for LSIs, new problems occur such as incomplete/illegal connections, delay faults that affect timing behavior, or crosstalk noise. In order to detect several types of faults described as various models, this research aims at enhancing defect coverage of test patterns for stuck-at faults, high quality test generation for delay faults, fault diagnosis, and fundamental techniques for these subjects. More specifically, we worked on the following five themes, and obtained results as follows :
(1) Research on improvement bridging fault coverage of test patterns for stuck-at faults.
Results : By identifying don't care bits in given test patterns for stuck-at faults, we developed a method to reassign logic values to the don't care bits so as to increase bridging fault coverage efficiently.
(2) Research on more precise test relaxation
Results : We developed a method that can identify more don't care bits than other methods published before. As an application of the developed method, we proposed a method of test cost reduction for full scan circuits.
(3) Research on high quality test for delay faults
Results : We developed a test generation method for transition delay faults and path delay faults respectively such that a test set with small size detects many faults.
(4) Research on fault diagnosis using X-fault model
Results : We developed a per-test fault diagnosis method using X-fault model that implies various fault models.
(5) Research on accelerating fault simulation techniques
Results : By combining a compiled logic simulation technique with an event-driven simulation technique, we developed fast fault simulator for logic circuits.

Report

(4 results)
  • 2006 Annual Research Report   Final Research Report Summary
  • 2005 Annual Research Report
  • 2004 Annual Research Report
  • Research Products

    (36 results)

All 2006 2005 2004

All Journal Article (33 results) Book (3 results)

  • [Journal Article] A statistical quality model for delay testing2006

    • Author(s)
      Yasuo Sato
    • Journal Title

      IEICE Trans. ELECTRONICS VOL. E89-C No. 3

      Pages: 349-355

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 多重スキャンツリー設計によるテストデータ量・テスト印加時間の削減2006

    • Author(s)
      宮瀬 紘平
    • Journal Title

      情報処理学会論文誌 Vol. 47 No. 6

      Pages: 1648-1657

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 統計的遅延品質モデル (SDQM) のフィージビリティ評価2006

    • Author(s)
      佐藤康夫
    • Journal Title

      電子情報通信学会論文誌 D-I Vol. J89-D-I No. 8

      Pages: 1717-1728

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Finding Don't Cares in Test Sequences for Sequential Circuits2006

    • Author(s)
      Yoshinobu Higami
    • Journal Title

      IEICE Trans. Info. & Syst. Vol. E89-D No. 11

      Pages: 2748-2755

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] A statistical quality model for delay testing2006

    • Author(s)
      Yasuo Sato
    • Journal Title

      IEICE Trans. ELECTRONICS VOL. E89-C-No. 3

      Pages: 349-355

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Reduction of Test Data Volume and Test Application Time with Multiple Scan Tree Design2006

    • Author(s)
      Kohei Miyase
    • Journal Title

      IPSJ Journal Vol. 47-No. 6

      Pages: 1648-1657

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Feasibility Evaluation of the Statical Delay Quality Model (SDQM)2006

    • Author(s)
      Yasuo Sato
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. J89-D-I-No. 8

      Pages: 1717-1728

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Finding Don't Cares in Test Sequences for Sequential Circuits2006

    • Author(s)
      Yoshinobu Higami
    • Journal Title

      IEICE Trans. Info. & Syst. Vol. E89-D-No. 11

      Pages: 2748-2755

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 多重スキャンツリー設計によるテストデータ量・テスト印加時間の削減2006

    • Author(s)
      宮瀬 紘平
    • Journal Title

      情報処理学会論文誌 47, 6

      Pages: 1648-1657

    • Related Report
      2006 Annual Research Report
  • [Journal Article] 統計的遅延品質モデル(SDQM)のフィージビリティ評価2006

    • Author(s)
      佐藤 康夫
    • Journal Title

      電子情報通信学会論文誌 D-I J89-D-I, 8

      Pages: 1717-1728

    • Related Report
      2006 Annual Research Report
  • [Journal Article] On Finding Don't Cares in Test Sequences for Sequential Circuits2006

    • Author(s)
      Higami, Yoshinobu
    • Journal Title

      IEICE Transactions on Information & Systems E89-D, 11

      Pages: 2748-2755

    • Related Report
      2006 Annual Research Report
  • [Journal Article] Hybrid fault simulation with compiled and event-driven methods2006

    • Author(s)
      Taniguchi, Kenjiro
    • Journal Title

      Proceedings of International Conference on Design & Test of Integrated Systems in Nanoscale Technology

      Pages: 240-243

    • Related Report
      2006 Annual Research Report
  • [Journal Article] A Framework of High-quality Transition Fault ATPG for Scan Circuits2006

    • Author(s)
      Kajihara, Seiji
    • Journal Title

      Proceedings of International Test Conference (CD-ROM)

      Pages: 6-6

    • Related Report
      2006 Annual Research Report
  • [Journal Article] A statistical quality model for delay testing2006

    • Author(s)
      Yasuo Sato, 他
    • Journal Title

      IEICE Trans.Electronics VOL.E89-C, No.3

      Pages: 349-355

    • Related Report
      2005 Annual Research Report
  • [Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005

    • Author(s)
      Xiaoqing WEN
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. E88-D No. 4

      Pages: 703-710

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005

    • Author(s)
      温 暁青
    • Journal Title

      電子情報通信学会論文誌 D-I Vol. J88-D-I No. 4

      Pages: 906-907

    • NAID

      10016599053

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis2005

    • Author(s)
      Masayasu Fukunaga
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. E88-D No. 7

      Pages: 1671-1677

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Three-Stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs2005

    • Author(s)
      Lei Li
    • Journal Title

      IEE Proc. Computers & Digital Technique Volume 152 Issue 6

      Pages: 704-712

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005

    • Author(s)
      Xiaoqing WEN
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. E88-D-No. 4

      Pages: 703-710

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Speed-Up of Fault Simulation for Handling Intermediate Faulty Voltages2005

    • Author(s)
      Xiaoqing WEN
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. J88-D-I-No. 4

      Pages: 906-907

    • NAID

      10016599053

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis2005

    • Author(s)
      Masayasu Fukunaga
    • Journal Title

      IEICE Trans. Info. and Syst. Vol. E88-D-No. 7

      Pages: 1671-1677

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Three-Stage Compression Approach to Reduce Test Data Volume and Testing Time for IP Cores in SOCs2005

    • Author(s)
      Lei Li
    • Journal Title

      IEE Proc. Computers & Digital Technique Volume 152-Issue 6

      Pages: 704-712

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies2005

    • Author(s)
      Xiaoqing WEN, 他
    • Journal Title

      IEICE Trans.Info.and Syst. Vol.E88-D, No.4

      Pages: 703-710

    • Related Report
      2005 Annual Research Report
  • [Journal Article] 中間故障電圧値を扱う故障シミュレーションの高速化について2005

    • Author(s)
      温 暁青, 他
    • Journal Title

      電子情報通信学会論文誌D-I Vol.J88-D-I, No.4

      Pages: 906-907

    • NAID

      10016599053

    • Related Report
      2005 Annual Research Report
  • [Journal Article] On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis.2005

    • Author(s)
      Masayasu Fukunaga, 他
    • Journal Title

      IEICE Trans.Info.and Syst. Vol.E88-D, No.7

      Pages: 1671-1677

    • Related Report
      2005 Annual Research Report
  • [Journal Article] Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation2005

    • Author(s)
      Y.Doi, S.Kajihara, X.Wen, L.Li, K.Chakrabarty
    • Journal Title

      Proceedings of Asia and South Pacific Design Automation Conference

      Pages: 59-64

    • NAID

      110003318193

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores2005

    • Author(s)
      L.Li, K.Chakrabarty, S.Kajihara, S.Swaminathan
    • Journal Title

      Proceedings of International Conference on VLSI Design

      Pages: 53-58

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Scan Tree Design : Test compression with Test Vector Modification2004

    • Author(s)
      Kohei Miyase
    • Journal Title

      情報処理学会論文誌 Vol. 44 No. 5

      Pages: 1270-1278

    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Scan Tree Design : Test compression with Test Vector Modification2004

    • Author(s)
      Kohei Miyase
    • Journal Title

      IPSJ Journal Vol. 44-No. 5

      Pages: 1270-1278

    • Description
      「研究成果報告書概要(欧文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Journal Article] Scan Tree Design : Test compression with Test Vector Modification2004

    • Author(s)
      Kohei Miyase, Seiji Kjihara
    • Journal Title

      情報処理学会論文誌 Vol.44 No.5

      Pages: 1270-1278

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values2004

    • Author(s)
      Seiji Kajihara, Kewal K.Saluja, Sudhakar M.Reddy
    • Journal Title

      Proceedings of 9^<th> IEEE European Test Symposium

      Pages: 108-113

    • Related Report
      2004 Annual Research Report
  • [Journal Article] On Per-Test Fault Diagnosis Using the X-Fault Model2004

    • Author(s)
      X.Wen, T.Miyoshi, S.Kajihara, L.T.Wang, K.K.Saluja, K.Kinoshita
    • Journal Title

      Proceedings of Int'l Conf.on Computer-Aided Design

      Pages: 633-640

    • Related Report
      2004 Annual Research Report
  • [Journal Article] Multiple Scan Tree Design with Test Vector Modification2004

    • Author(s)
      Kohei Miyase, Seiji Kajihara, Sudhakar M.Reddy
    • Journal Title

      Proceedings of Asian Test Symposium

      Pages: 76-81

    • Related Report
      2004 Annual Research Report
  • [Book] IT TEXT システムLSI設計工学2006

    • Author(s)
      藤田昌弘
    • Total Pages
      231
    • Publisher
      オーム社
    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Annual Research Report 2006 Final Research Report Summary
  • [Book] ディペンダブルシステム2005

    • Author(s)
      米田友洋
    • Total Pages
      243
    • Publisher
      共立出版
    • Description
      「研究成果報告書概要(和文)」より
    • Related Report
      2006 Final Research Report Summary
  • [Book] ディペンダブルシステム2005

    • Author(s)
      米田友洋, 梶原誠司, 土屋達弘
    • Total Pages
      243
    • Publisher
      共立出版
    • Related Report
      2005 Annual Research Report

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Published: 2004-04-01   Modified: 2016-04-21  

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