Study on LSI testing for multiple fault models
| Project/Area Number |
16500036
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu Institute of Technology |
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Principal Investigator |
KAJIHARA Seiji Kyushu Institute of Technology, Faculty of Computer Science and Systems Engineering, Professor, 情報工学部, 教授 (80252592)
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| Co-Investigator(Kenkyū-buntansha) |
WEN Xiaoqing Kyushu Institute of Technology, Graduate School of Computer Science and Systems Engineering, Associate Professor, 大学院情報工学研究科, 助教授 (20250897)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2006: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 2005: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2004: ¥1,900,000 (Direct Cost: ¥1,900,000)
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| Keywords | design and test of LSIs / logic circuit / test pattern generation / fault diagnosis / bridging fault / delay fault / dependability / fault simulation / テスト生成 / システムオンチップ / 計算機システム / ディペンダブル・コンピューティング / X故障モデル / N回検出テスト |
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| Research Abstract |
With the progress of design and manufacturing technology for LSIs, new problems occur such as incomplete/illegal connections, delay faults that affect timing behavior, or crosstalk noise. In order to detect several types of faults described as various models, this research aims at enhancing defect coverage of test patterns for stuck-at faults, high quality test generation for delay faults, fault diagnosis, and fundamental techniques for these subjects. More specifically, we worked on the following five themes, and obtained results as follows :
(1) Research on improvement bridging fault coverage of test patterns for stuck-at faults.
Results : By identifying don't care bits in given test patterns for stuck-at faults, we developed a method to reassign logic values to the don't care bits so as to increase bridging fault coverage efficiently.
(2) Research on more precise test relaxation
Results : We developed a method that can identify more don't care bits than other methods published before. As an application of the developed method, we proposed a method of test cost reduction for full scan circuits.
(3) Research on high quality test for delay faults
Results : We developed a test generation method for transition delay faults and path delay faults respectively such that a test set with small size detects many faults.
(4) Research on fault diagnosis using X-fault model
Results : We developed a per-test fault diagnosis method using X-fault model that implies various fault models.
(5) Research on accelerating fault simulation techniques
Results : By combining a compiled logic simulation technique with an event-driven simulation technique, we developed fast fault simulator for logic circuits.
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Report
(4 results)
Research Products
(36 results)
