| Project/Area Number |
16500041
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Shibaura Institute of Technology |
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Principal Investigator |
USAMI Kimiyoshi Shibaura Institute of Technology, Engineering Department, Professor, 工学部, 教授 (20365547)
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| Project Period (FY) |
2004 – 2006
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| Project Status |
Completed (Fiscal Year 2006)
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| Budget Amount *help |
¥3,600,000 (Direct Cost: ¥3,600,000)
Fiscal Year 2006: ¥600,000 (Direct Cost: ¥600,000)
Fiscal Year 2005: ¥900,000 (Direct Cost: ¥900,000)
Fiscal Year 2004: ¥2,100,000 (Direct Cost: ¥2,100,000)
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| Keywords | Low power / Architecture / Leakage power / FPGA |
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| Research Abstract |
Objective of this study is to research architecture, hardware structure and control scheme to effectively reduce power dissipation of computer systems. Design techniques for leakage-power reduction and low-power methodology for Field Programmable Gate Array (FPGA) have been focused.
For leakage power reduction, I studied an approach to turn off power switches of circuit components by automatically detecting time intervals that do not require operations of the circuit components. As a micro-architecture level technique, I focused on an approach to put the execution unit into sleep by detecting pipeline stalls. Results from investigating with a pipeline simulator of SH3 microprocessor showed that the execution unit can be put into sleep at most 60% of the total execution time at the Dhrystone program. Furthermore, I proposed a technique to implement an LSI by partitioning into fine-grained power domains using gated-clock enable signals. Simulation results from applying the CPU datapath showed that active leakage power reduced by approximately 50% at 1% power overhead due to power switches in 90nm devices.
In the study on power reduction techniques for FPGA, I first conducted detailed analysis on power dissipation inside commercial FPGAs. Results showed that 70-80% of the power is consumed in interconnections. This motivated me to research design approaches to reduce power in interconnections in FPGA. I proposed and evaluated a methodology to add placement constraints so that the wire length with large switching activity be shortened with higher priority. Moreover, I studied a design methodology to use two different supply voltages at interconnections for reducing power. Results showed that it reduced power by 30-50% compared with the conventional single power-supply design.
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